--- /dev/null
+#include <linux/module.h>\r
+#include <linux/kernel.h>\r
+#include <linux/errno.h>\r
+#include <linux/string.h>\r
+#include <linux/mm.h>\r
+#include <linux/slab.h>\r
+#include <linux/delay.h>\r
+#include <linux/device.h>\r
+#include <linux/init.h>\r
+#include <linux/dma-mapping.h>\r
+#include <linux/interrupt.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/clk.h>\r
+#include <linux/backlight.h>\r
+#include <linux/timer.h>\r
+#include <linux/time.h>\r
+#include <linux/wait.h>\r
+#include <linux/earlysuspend.h>\r
+#include <linux/cpufreq.h>\r
+#include <linux/wakelock.h>\r
+\r
+#include <asm/io.h>\r
+#include <asm/div64.h>\r
+#include <asm/uaccess.h>\r
+\r
+\r
+#include <mach/iomux.h>\r
+#include <mach/gpio.h>\r
+#include <mach/board.h>\r
+#include <mach/rk29_iomap.h>\r
+#include <mach/pmu.h>\r
+\r
+void __iomem *rank0_vir_base; // virtual basic address of lcdc register\r
+struct clk *smc_clk = NULL;\r
+struct clk *smc_axi_clk = NULL;\r
+void __iomem *reg_vir_base; // virtual basic address of lcdc register\r
+\r
+int smc0_enable(int enable)\r
+{\r
+ if(enable){\r
+ clk_enable(smc_axi_clk);\r
+ clk_enable(smc_clk);\r
+ __raw_writel(__raw_readl(RK29_GRF_BASE+0xbc) | 0x2000 , (RK29_GRF_BASE+0xbc));\r
+\r
+ __raw_writel((0x801), (reg_vir_base+0x18));\r
+ __raw_writel(0x00400000, (reg_vir_base+0x10));\r
+ __raw_writel((15 | (14<<8) | (15<<4) | (5<<11) ), (reg_vir_base+0x14));\r
+ //__raw_writel((15 | (10<<8) | (15<<4) | (7<<11) ), (reg_vir_base+0x14));\r
+\r
+ __raw_writel(0x00400000, (reg_vir_base+0x10));\r
+ } else {\r
+ clk_disable(smc_axi_clk);\r
+ clk_disable(smc_clk);\r
+ }\r
+ return 0;\r
+}\r
+\r
+int smc0_init(u8 **base_addr)\r
+{\r
+ u32 reg_phy_base; // physical basic address of lcdc register\r
+ u32 len; // physical map length of lcdc register\r
+ struct resource *mem;\r
+\r
+ u32 rank0_phy_base; // physical basic address of lcdc register\r
+ u32 rank0_len; // physical map length of lcdc register\r
+ struct resource *rank0_mem;\r
+\r
+ printk(" %s %d \n",__FUNCTION__, __LINE__);\r
+\r
+ if(smc_axi_clk == NULL)smc_axi_clk = clk_get(NULL, "aclk_smc");\r
+ if(smc_clk == NULL)smc_clk = clk_get(NULL, "smc");\r
+\r
+ rank0_phy_base = 0x11000000; //0x12000000;//\r
+ rank0_len = SZ_4K;\r
+ rank0_mem = request_mem_region(rank0_phy_base, rank0_len, "smc_rank0");\r
+ if (rank0_mem == NULL)\r
+ {\r
+ printk("failed to get rank0 memory region [%d]\n",__LINE__);\r
+ }\r
+\r
+ rank0_vir_base = ioremap(rank0_phy_base, rank0_len);\r
+ if (rank0_vir_base == NULL)\r
+ {\r
+ printk("ioremap() of rank0 failed\n");\r
+ }\r
+\r
+ //*base_addr = rank0_vir_base;\r
+\r
+ reg_phy_base = RK29_SMC_PHYS;\r
+ len = SZ_16K;\r
+ mem = request_mem_region(reg_phy_base, len, "smc reg");\r
+ if (mem == NULL)\r
+ {\r
+ printk("failed to get memory region [%d]\n",__LINE__);\r
+ }\r
+\r
+ reg_vir_base = ioremap(reg_phy_base, len);\r
+ if (reg_vir_base == NULL)\r
+ {\r
+ printk("ioremap() of registers failed\n");\r
+ }\r
+\r
+ smc0_enable(1);\r
+\r
+ rk29_mux_api_set(GPIO0B7_EBCGDOE_SMCOEN_NAME, GPIO0L_SMC_OE_N);\r
+ rk29_mux_api_set(GPIO0B6_EBCSDSHR_SMCBLSN1_HOSTINT_NAME, GPIO0L_SMC_BLS_N_1 );\r
+ rk29_mux_api_set(GPIO0B5_EBCVCOM_SMCBLSN0_NAME, GPIO0L_SMC_BLS_N_0 );\r
+ rk29_mux_api_set(GPIO0B4_EBCBORDER1_SMCWEN_NAME, GPIO0L_SMC_WE_N);\r
+\r
+ rk29_mux_api_set(GPIO0B3_EBCBORDER0_SMCADDR3_HOSTDATA3_NAME, GPIO0L_SMC_ADDR3);\r
+ rk29_mux_api_set(GPIO0B2_EBCSDCE2_SMCADDR2_HOSTDATA2_NAME, GPIO0L_SMC_ADDR2);\r
+ rk29_mux_api_set(GPIO0B1_EBCSDCE1_SMCADDR1_HOSTDATA1_NAME, GPIO0L_SMC_ADDR1);\r
+ rk29_mux_api_set(GPIO0B0_EBCSDCE0_SMCADDR0_HOSTDATA0_NAME, GPIO0L_SMC_ADDR0);\r
+\r
+ rk29_mux_api_set(GPIO1A1_SMCCSN0_NAME, GPIO1L_SMC_CSN0);\r
+ // rk29_mux_api_set(GPIO1A1_SMCCSN0_NAME, GPIO1L_GPIO1A1);\r
+\r
+ // if(gpio_request(RK29_PIN1_PA1, NULL) != 0)\r
+ {\r
+ // gpio_free(RK29_PIN1_PA1);\r
+ // printk(">>>>>> RK29_PIN1_PA1 gpio_request err \n ");\r
+ }\r
+ // gpio_direction_output(RK29_PIN1_PA1, GPIO_LOW);\r
+\r
+ rk29_mux_api_set(GPIO1A2_SMCCSN1_NAME, GPIO1L_SMC_CSN1);\r
+ rk29_mux_api_set(GPIO0D0_EBCSDOE_SMCADVN_NAME, GPIO0H_SMC_ADV_N);\r
+\r
+ rk29_mux_api_set(GPIO5C0_EBCSDDO0_SMCDATA0_NAME, GPIO5H_SMC_DATA0);\r
+ rk29_mux_api_set(GPIO5C1_EBCSDDO1_SMCDATA1_NAME, GPIO5H_SMC_DATA1);\r
+ rk29_mux_api_set(GPIO5C2_EBCSDDO2_SMCDATA2_NAME, GPIO5H_SMC_DATA2);\r
+ rk29_mux_api_set(GPIO5C3_EBCSDDO3_SMCDATA3_NAME, GPIO5H_SMC_DATA3);\r
+ rk29_mux_api_set(GPIO5C4_EBCSDDO4_SMCDATA4_NAME, GPIO5H_SMC_DATA4);\r
+ rk29_mux_api_set(GPIO5C5_EBCSDDO5_SMCDATA5_NAME, GPIO5H_SMC_DATA5);\r
+ rk29_mux_api_set(GPIO5C6_EBCSDDO6_SMCDATA6_NAME, GPIO5H_SMC_DATA6);\r
+ rk29_mux_api_set(GPIO5C7_EBCSDDO7_SMCDATA7_NAME, GPIO5H_SMC_DATA7);\r
+\r
+ rk29_mux_api_set(GPIO0C0_EBCGDSP_SMCDATA8_NAME, GPIO0H_SMC_DATA8);\r
+ rk29_mux_api_set(GPIO0C1_EBCGDR1_SMCDATA9_NAME, GPIO0H_SMC_DATA9);\r
+ rk29_mux_api_set(GPIO0C2_EBCSDCE0_SMCDATA10_NAME, GPIO0H_SMC_DATA10);\r
+ rk29_mux_api_set(GPIO0C3_EBCSDCE1_SMCDATA11_NAME, GPIO0H_SMC_DATA11);\r
+ rk29_mux_api_set(GPIO0C4_EBCSDCE2_SMCDATA12_NAME, GPIO0H_SMC_DATA12);\r
+ rk29_mux_api_set(GPIO0C5_EBCSDCE3_SMCDATA13_NAME, GPIO0H_SMC_DATA13);\r
+ rk29_mux_api_set(GPIO0C6_EBCSDCE4_SMCDATA14_NAME, GPIO0H_SMC_DATA14);\r
+ rk29_mux_api_set(GPIO0C7_EBCSDCE5_SMCDATA15_NAME, GPIO0H_SMC_DATA15);\r
+\r
+ return 0;\r
+\r
+}\r
+\r
+\r
+\r
+int smc0_write(u32 addr, u16 data)\r
+{\r
+ // __raw_writel(data, rank0_vir_base + addr);\r
+ u16 *p = rank0_vir_base + addr;\r
+ int readdata;\r
+ *p = data;\r
+ udelay(5);\r
+ //readdata = *p;\r
+ //mdelay(5);\r
+ //mdelay(10);\r
+ //printk("%s addr=%x, data = %x, read date = %x\n",__FUNCTION__,addr,data,readdata);\r
+ return 0;\r
+}\r
+\r
+int smc0_read(u32 addr)\r
+{\r
+ u16 * p = rank0_vir_base + addr;\r
+ int readdata = *p; \r
+ //mdelay(5);\r
+ //printk("%s addr=%x, read date = %x\n",__FUNCTION__,addr,readdata);\r
+ return readdata;//__raw_readl(rank0_vir_base + addr);\r
+}\r
+\r
+void smc0_exit(void)\r
+{\r
+ smc0_enable(0);\r
+}\r
+\r
+\r
+\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff