#include "ni_tio.h"
-#define _bit15 0x8000
-#define _bit14 0x4000
-#define _bit13 0x2000
-#define _bit12 0x1000
-#define _bit11 0x0800
-#define _bit10 0x0400
-#define _bit9 0x0200
-#define _bit8 0x0100
-#define _bit7 0x0080
-#define _bit6 0x0040
-#define _bit5 0x0020
-#define _bit4 0x0010
-#define _bit3 0x0008
-#define _bit2 0x0004
-#define _bit1 0x0002
-#define _bit0 0x0001
-
-#define NUM_PFI_OUTPUT_SELECT_REGS 6
-
/*
* Registers in the National Instruments DAQ-STC chip
*/
#define NISTC_INTB_ENA_AO_START1 BIT(1)
#define NISTC_INTB_ENA_AO_BC_TC BIT(0)
-#define AI_Status_1_Register 2
-#define Interrupt_A_St 0x8000
-#define AI_FIFO_Full_St 0x4000
-#define AI_FIFO_Half_Full_St 0x2000
-#define AI_FIFO_Empty_St 0x1000
-#define AI_Overrun_St 0x0800
-#define AI_Overflow_St 0x0400
-#define AI_SC_TC_Error_St 0x0200
-#define AI_START2_St 0x0100
-#define AI_START1_St 0x0080
-#define AI_SC_TC_St 0x0040
-#define AI_START_St 0x0020
-#define AI_STOP_St 0x0010
-#define G0_TC_St 0x0008
-#define G0_Gate_Interrupt_St 0x0004
-#define AI_FIFO_Request_St 0x0002
-#define Pass_Thru_0_Interrupt_St 0x0001
-
-#define AI_Status_2_Register 5
-
-#define AO_Status_1_Register 3
-#define Interrupt_B_St _bit15
-#define AO_FIFO_Full_St _bit14
-#define AO_FIFO_Half_Full_St _bit13
-#define AO_FIFO_Empty_St _bit12
-#define AO_BC_TC_Error_St _bit11
-#define AO_START_St _bit10
-#define AO_Overrun_St _bit9
-#define AO_START1_St _bit8
-#define AO_BC_TC_St _bit7
-#define AO_UC_TC_St _bit6
-#define AO_UPDATE_St _bit5
-#define AO_UI2_TC_St _bit4
-#define G1_TC_St _bit3
-#define G1_Gate_Interrupt_St _bit2
-#define AO_FIFO_Request_St _bit1
-#define Pass_Thru_1_Interrupt_St _bit0
-
-#define AO_Status_2_Register 6
-
-#define DIO_Parallel_Input_Register 7
-
-#define AI_SI_Save_Registers 64
-#define AI_SC_Save_Registers 66
-
-#define Joint_Status_1_Register 27
-#define DIO_Serial_IO_In_Progress_St _bit12
-
-#define DIO_Serial_Input_Register 28
-#define Joint_Status_2_Register 29
-enum Joint_Status_2_Bits {
- AO_TMRDACWRs_In_Progress_St = 0x20,
-};
+#define NISTC_AI_PERSONAL_REG 77
+#define NISTC_AI_PERSONAL_SHIFTIN_PW BIT(15)
+#define NISTC_AI_PERSONAL_EOC_POLARITY BIT(14)
+#define NISTC_AI_PERSONAL_SOC_POLARITY BIT(13)
+#define NISTC_AI_PERSONAL_SHIFTIN_POL BIT(12)
+#define NISTC_AI_PERSONAL_CONVERT_TIMEBASE BIT(11)
+#define NISTC_AI_PERSONAL_CONVERT_PW BIT(10)
+#define NISTC_AI_PERSONAL_CONVERT_ORIG_PULSE BIT(9)
+#define NISTC_AI_PERSONAL_FIFO_FLAGS_POL BIT(8)
+#define NISTC_AI_PERSONAL_OVERRUN_MODE BIT(7)
+#define NISTC_AI_PERSONAL_EXTMUX_CLK_PW BIT(6)
+#define NISTC_AI_PERSONAL_LOCALMUX_CLK_PW BIT(5)
+#define NISTC_AI_PERSONAL_AIFREQ_POL BIT(4)
+
+#define NISTC_AO_PERSONAL_REG 78
+#define NISTC_AO_PERSONAL_MULTI_DACS BIT(15) /* M-Series only */
+#define NISTC_AO_PERSONAL_NUM_DAC BIT(14) /* 1:single; 0:dual */
+#define NISTC_AO_PERSONAL_FAST_CPU BIT(13) /* M-Series reserved */
+#define NISTC_AO_PERSONAL_TMRDACWR_PW BIT(12)
+#define NISTC_AO_PERSONAL_FIFO_FLAGS_POL BIT(11) /* M-Series reserved */
+#define NISTC_AO_PERSONAL_FIFO_ENA BIT(10)
+#define NISTC_AO_PERSONAL_AOFREQ_POL BIT(9) /* M-Series reserved */
+#define NISTC_AO_PERSONAL_DMA_PIO_CTRL BIT(8) /* M-Series reserved */
+#define NISTC_AO_PERSONAL_UPDATE_ORIG_PULSE BIT(7)
+#define NISTC_AO_PERSONAL_UPDATE_TIMEBASE BIT(6)
+#define NISTC_AO_PERSONAL_UPDATE_PW BIT(5)
+#define NISTC_AO_PERSONAL_BC_SRC_SEL BIT(4)
+#define NISTC_AO_PERSONAL_INTERVAL_BUFFER_MODE BIT(3)
+
+#define NISTC_RTSI_TRIGA_OUT_REG 79
+#define NISTC_RTSI_TRIGB_OUT_REG 80
+#define NISTC_RTSI_TRIGB_SUB_SEL1 BIT(15) /* not for M-Series */
+#define NISTC_RTSI_TRIG(_c, _s) (((_s) & 0xf) << (((_c) % 4) * 4))
+#define NISTC_RTSI_TRIG_MASK(_c) NISTC_RTSI_TRIG((_c), 0xf)
+#define NISTC_RTSI_TRIG_TO_SRC(_c, _b) (((_b) >> (((_c) % 4) * 4)) & 0xf)
+
+#define NISTC_RTSI_BOARD_REG 81
+
+#define NISTC_CFG_MEM_CLR_REG 82
+#define NISTC_ADC_FIFO_CLR_REG 83
+#define NISTC_DAC_FIFO_CLR_REG 84
+#define NISTC_WR_STROBE3_REG 85
+
+#define NISTC_AO_OUT_CTRL_REG 86
+#define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15)
+#define NISTC_AO_OUT_CTRL_EXT_GATE_SEL(x) (((x) & 0x1f) << 10)
+#define NISTC_AO_OUT_CTRL_CHANS(x) (((x) & 0xf) << 6)
+#define NISTC_AO_OUT_CTRL_UPDATE2_SEL(x) (((x) & 0x3) << 4)
+#define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3)
+#define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL(x) (((x) & 0x3) << 0)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ NISTC_AO_OUT_CTRL_UPDATE_SEL(0)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL_GND NISTC_AO_OUT_CTRL_UPDATE_SEL(1)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL_LOW NISTC_AO_OUT_CTRL_UPDATE_SEL(2)
+#define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGH NISTC_AO_OUT_CTRL_UPDATE_SEL(3)
+
+#define NISTC_AI_MODE3_REG 87
+#define NISTC_AI_MODE3_TRIG_LEN BIT(15)
+#define NISTC_AI_MODE3_DELAY_START BIT(14)
+#define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13)
+#define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12)
+#define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11)
+#define NISTC_AI_MODE3_DELAYED_START2 BIT(10)
+#define NISTC_AI_MODE3_DELAYED_START1 BIT(9)
+#define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8)
+#define NISTC_AI_MODE3_FIFO_MODE(x) (((x) & 0x3) << 6)
+#define NISTC_AI_MODE3_FIFO_MODE_NE NISTC_AI_MODE3_FIFO_MODE(0)
+#define NISTC_AI_MODE3_FIFO_MODE_HF NISTC_AI_MODE3_FIFO_MODE(1)
+#define NISTC_AI_MODE3_FIFO_MODE_F NISTC_AI_MODE3_FIFO_MODE(2)
+#define NISTC_AI_MODE3_FIFO_MODE_HF_E NISTC_AI_MODE3_FIFO_MODE(3)
+#define NISTC_AI_MODE3_EXT_GATE_POL BIT(5)
+#define NISTC_AI_MODE3_EXT_GATE_SEL(x) (((x) & 0x1f) << 0)
+
+#define NISTC_AI_STATUS1_REG 2
+#define NISTC_AI_STATUS1_INTA BIT(15)
+#define NISTC_AI_STATUS1_FIFO_F BIT(14)
+#define NISTC_AI_STATUS1_FIFO_HF BIT(13)
+#define NISTC_AI_STATUS1_FIFO_E BIT(12)
+#define NISTC_AI_STATUS1_OVERRUN BIT(11)
+#define NISTC_AI_STATUS1_OVERFLOW BIT(10)
+#define NISTC_AI_STATUS1_SC_TC_ERR BIT(9)
+#define NISTC_AI_STATUS1_OVER (NISTC_AI_STATUS1_OVERRUN | \
+ NISTC_AI_STATUS1_OVERFLOW)
+#define NISTC_AI_STATUS1_ERR (NISTC_AI_STATUS1_OVER | \
+ NISTC_AI_STATUS1_SC_TC_ERR)
+#define NISTC_AI_STATUS1_START2 BIT(8)
+#define NISTC_AI_STATUS1_START1 BIT(7)
+#define NISTC_AI_STATUS1_SC_TC BIT(6)
+#define NISTC_AI_STATUS1_START BIT(5)
+#define NISTC_AI_STATUS1_STOP BIT(4)
+#define NISTC_AI_STATUS1_G0_TC BIT(3)
+#define NISTC_AI_STATUS1_G0_GATE BIT(2)
+#define NISTC_AI_STATUS1_FIFO_REQ BIT(1)
+#define NISTC_AI_STATUS1_PASSTHRU0 BIT(0)
+
+#define NISTC_AO_STATUS1_REG 3
+#define NISTC_AO_STATUS1_INTB BIT(15)
+#define NISTC_AO_STATUS1_FIFO_F BIT(14)
+#define NISTC_AO_STATUS1_FIFO_HF BIT(13)
+#define NISTC_AO_STATUS1_FIFO_E BIT(12)
+#define NISTC_AO_STATUS1_BC_TC_ERR BIT(11)
+#define NISTC_AO_STATUS1_START BIT(10)
+#define NISTC_AO_STATUS1_OVERRUN BIT(9)
+#define NISTC_AO_STATUS1_START1 BIT(8)
+#define NISTC_AO_STATUS1_BC_TC BIT(7)
+#define NISTC_AO_STATUS1_UC_TC BIT(6)
+#define NISTC_AO_STATUS1_UPDATE BIT(5)
+#define NISTC_AO_STATUS1_UI2_TC BIT(4)
+#define NISTC_AO_STATUS1_G1_TC BIT(3)
+#define NISTC_AO_STATUS1_G1_GATE BIT(2)
+#define NISTC_AO_STATUS1_FIFO_REQ BIT(1)
+#define NISTC_AO_STATUS1_PASSTHRU1 BIT(0)
+
+#define NISTC_G01_STATUS_REG 4
+
+#define NISTC_AI_STATUS2_REG 5
+
+#define NISTC_AO_STATUS2_REG 6
+
+#define NISTC_DIO_IN_REG 7
+
+#define NISTC_G0_HW_SAVE_REG 8
+#define NISTC_G1_HW_SAVE_REG 10
+
+#define NISTC_G0_SAVE_REG 12
+#define NISTC_G1_SAVE_REG 14
+
+#define NISTC_AO_UI_SAVE_REG 16
+#define NISTC_AO_BC_SAVE_REG 18
+#define NISTC_AO_UC_SAVE_REG 20
+
+#define NISTC_STATUS1_REG 27
+#define NISTC_STATUS1_SERIO_IN_PROG BIT(12)
+
+#define NISTC_DIO_SERIAL_IN_REG 28
+
+#define NISTC_STATUS2_REG 29
+#define NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS BIT(5)
+
+#define NISTC_AI_SI_SAVE_REG 64
+#define NISTC_AI_SC_SAVE_REG 66
-#define AO_UI_Save_Registers 16
-#define AO_BC_Save_Registers 18
-#define AO_UC_Save_Registers 20
-
-#define AI_Personal_Register 77
-#define AI_SHIFTIN_Pulse_Width _bit15
-#define AI_EOC_Polarity _bit14
-#define AI_SOC_Polarity _bit13
-#define AI_SHIFTIN_Polarity _bit12
-#define AI_CONVERT_Pulse_Timebase _bit11
-#define AI_CONVERT_Pulse_Width _bit10
-#define AI_CONVERT_Original_Pulse _bit9
-#define AI_FIFO_Flags_Polarity _bit8
-#define AI_Overrun_Mode _bit7
-#define AI_EXTMUX_CLK_Pulse_Width _bit6
-#define AI_LOCALMUX_CLK_Pulse_Width _bit5
-#define AI_AIFREQ_Polarity _bit4
-
-#define AO_Personal_Register 78
-enum AO_Personal_Bits {
- AO_Interval_Buffer_Mode = 1 << 3,
- AO_BC_Source_Select = 1 << 4,
- AO_UPDATE_Pulse_Width = 1 << 5,
- AO_UPDATE_Pulse_Timebase = 1 << 6,
- AO_UPDATE_Original_Pulse = 1 << 7,
- AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */
- AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */
- AO_FIFO_Enable = 1 << 10,
- AO_FIFO_Flags_Polarity = 1 << 11, /* M Series: reserved */
- AO_TMRDACWR_Pulse_Width = 1 << 12,
- AO_Fast_CPU = 1 << 13, /* M Series: reserved */
- AO_Number_Of_DAC_Packages = 1 << 14, /* 1 for "single" mode, 0 for "dual" */
- AO_Multiple_DACS_Per_Package = 1 << 15 /* m-series only */
-};
-#define RTSI_Trig_A_Output_Register 79
-#define RTSI_Trig_B_Output_Register 80
-enum RTSI_Trig_B_Output_Bits {
- RTSI_Sub_Selection_1_Bit = 0x8000 /* not for m-series */
-};
-static inline unsigned RTSI_Trig_Output_Bits(unsigned rtsi_channel,
- unsigned source)
-{
- return (source & 0xf) << ((rtsi_channel % 4) * 4);
-};
-
-static inline unsigned RTSI_Trig_Output_Mask(unsigned rtsi_channel)
-{
- return 0xf << ((rtsi_channel % 4) * 4);
-};
-
-/* inverse to RTSI_Trig_Output_Bits() */
-static inline unsigned RTSI_Trig_Output_Source(unsigned rtsi_channel,
- unsigned bits)
-{
- return (bits >> ((rtsi_channel % 4) * 4)) & 0xf;
-};
+/*
+ * PCI E Series Registers
+ */
+#define NI_E_STC_WINDOW_ADDR_REG 0x00 /* rw16 */
+#define NI_E_STC_WINDOW_DATA_REG 0x02 /* rw16 */
+
+#define NI_E_STATUS_REG 0x01 /* r8 */
+#define NI_E_STATUS_AI_FIFO_LOWER_NE BIT(3)
+#define NI_E_STATUS_PROMOUT BIT(0)
+
+#define NI_E_DMA_AI_AO_SEL_REG 0x09 /* w8 */
+#define NI_E_DMA_AI_SEL(x) (((x) & 0xf) << 0)
+#define NI_E_DMA_AI_SEL_MASK NI_E_DMA_AI_SEL(0xf)
+#define NI_E_DMA_AO_SEL(x) (((x) & 0xf) << 4)
+#define NI_E_DMA_AO_SEL_MASK NI_E_DMA_AO_SEL(0xf)
+
+#define NI_E_DMA_G0_G1_SEL_REG 0x0b /* w8 */
+#define NI_E_DMA_G0_G1_SEL(_g, _c) (((_c) & 0xf) << ((_g) * 4))
+#define NI_E_DMA_G0_G1_SEL_MASK(_g) NI_E_DMA_G0_G1_SEL((_g), 0xf)
+
+#define NI_E_SERIAL_CMD_REG 0x0d /* w8 */
+#define NI_E_SERIAL_CMD_DAC_LD(x) BIT(3 + (x))
+#define NI_E_SERIAL_CMD_EEPROM_CS BIT(2)
+#define NI_E_SERIAL_CMD_SDATA BIT(1)
+#define NI_E_SERIAL_CMD_SCLK BIT(0)
+
+#define NI_E_MISC_CMD_REG 0x0f /* w8 */
+#define NI_E_MISC_CMD_INTEXT_ATRIG(x) (((x) & 0x1) << 7)
+#define NI_E_MISC_CMD_EXT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(0)
+#define NI_E_MISC_CMD_INT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(1)
+
+#define NI_E_AI_CFG_LO_REG 0x10 /* w16 */
+#define NI_E_AI_CFG_LO_LAST_CHAN BIT(15)
+#define NI_E_AI_CFG_LO_GEN_TRIG BIT(12)
+#define NI_E_AI_CFG_LO_DITHER BIT(9)
+#define NI_E_AI_CFG_LO_UNI BIT(8)
+#define NI_E_AI_CFG_LO_GAIN(x) ((x) << 0)
+
+#define NI_E_AI_CFG_HI_REG 0x12 /* w16 */
+#define NI_E_AI_CFG_HI_TYPE(x) (((x) & 0x7) << 12)
+#define NI_E_AI_CFG_HI_TYPE_DIFF NI_E_AI_CFG_HI_TYPE(1)
+#define NI_E_AI_CFG_HI_TYPE_COMMON NI_E_AI_CFG_HI_TYPE(2)
+#define NI_E_AI_CFG_HI_TYPE_GROUND NI_E_AI_CFG_HI_TYPE(3)
+#define NI_E_AI_CFG_HI_AC_COUPLE BIT(11)
+#define NI_E_AI_CFG_HI_CHAN(x) (((x) & 0x3f) << 0)
+
+#define NI_E_AO_CFG_REG 0x16 /* w16 */
+#define NI_E_AO_DACSEL(x) ((x) << 8)
+#define NI_E_AO_GROUND_REF BIT(3)
+#define NI_E_AO_EXT_REF BIT(2)
+#define NI_E_AO_DEGLITCH BIT(1)
+#define NI_E_AO_CFG_BIP BIT(0)
+
+#define NI_E_DAC_DIRECT_DATA_REG(x) (0x18 + ((x) * 2)) /* w16 */
+
+#define NI_E_8255_BASE 0x19 /* rw8 */
+
+#define NI_E_AI_FIFO_DATA_REG 0x1c /* r16 */
+
+#define NI_E_AO_FIFO_DATA_REG 0x1e /* w16 */
-#define RTSI_Board_Register 81
-#define Write_Strobe_0_Register 82
-#define Write_Strobe_1_Register 83
-#define Write_Strobe_2_Register 84
-#define Write_Strobe_3_Register 85
-
-#define AO_Output_Control_Register 86
-#define AO_External_Gate_Enable _bit15
-#define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
-#define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
-#define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
-#define AO_External_Gate_Polarity _bit3
-#define AO_UPDATE2_Output_Toggle _bit2
-enum ao_update_output_selection {
- AO_Update_Output_High_Z = 0,
- AO_Update_Output_Ground = 1,
- AO_Update_Output_Enable_Low = 2,
- AO_Update_Output_Enable_High = 3
-};
-static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection
- selection)
-{
- return selection & 0x3;
-}
-
-#define AI_Mode_3_Register 87
-#define AI_Trigger_Length _bit15
-#define AI_Delay_START _bit14
-#define AI_Software_Gate _bit13
-#define AI_SI_Special_Trigger_Delay _bit12
-#define AI_SI2_Source_Select _bit11
-#define AI_Delayed_START2 _bit10
-#define AI_Delayed_START1 _bit9
-#define AI_External_Gate_Mode _bit8
-#define AI_FIFO_Mode_HF_to_E (3<<6)
-#define AI_FIFO_Mode_F (2<<6)
-#define AI_FIFO_Mode_HF (1<<6)
-#define AI_FIFO_Mode_NE (0<<6)
-#define AI_External_Gate_Polarity _bit5
-#define AI_External_Gate_Select(a) ((a) & 0x1f)
-
-#define G_HW_Save_Register(a) (8+(a)*2)
-#define G_HW_Save_Register_High(a) (8+(a)*2)
-#define G_HW_Save_Register_Low(a) (9+(a)*2)
-#define G_Save_Register(a) (12+(a)*2)
-#define G_Save_Register_High(a) (12+(a)*2)
-#define G_Save_Register_Low(a) (13+(a)*2)
-#define G_Status_Register 4
-
-/* command register */
-#define G_Disarm_Copy _bit15 /* strobe */
-#define G_Save_Trace_Copy _bit14
-#define G_Arm_Copy _bit13 /* strobe */
-#define G_Bank_Switch_Start _bit10 /* strobe */
-#define G_Little_Big_Endian _bit9
-#define G_Synchronized_Gate _bit8
-#define G_Write_Switch _bit7
-#define G_Up_Down(a) (((a)&0x03)<<5)
-#define G_Disarm _bit4 /* strobe */
-#define G_Analog_Trigger_Reset _bit3 /* strobe */
-#define G_Save_Trace _bit1
-#define G_Arm _bit0 /* strobe */
-
-/*channel agnostic names for the command register #defines */
-#define G_Bank_Switch_Enable _bit12
-#define G_Bank_Switch_Mode _bit11
-#define G_Load _bit2 /* strobe */
-
-/* input select register */
-#define G_Gate_Select(a) (((a)&0x1f)<<7)
-#define G_Source_Select(a) (((a)&0x1f)<<2)
-#define G_Write_Acknowledges_Irq _bit1
-#define G_Read_Acknowledges_Irq _bit0
-
-/* same input select register, but with channel agnostic names */
-#define G_Source_Polarity _bit15
-#define G_Output_Polarity _bit14
-#define G_OR_Gate _bit13
-#define G_Gate_Select_Load_Source _bit12
-
-/* mode register */
-#define G_Loading_On_TC _bit12
-#define G_Output_Mode(a) (((a)&0x03)<<8)
-#define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
-#define G_Gating_Mode(a) (((a)&0x03)<<0)
-
-/* same input mode register, but with channel agnostic names */
-#define G_Load_Source_Select _bit7
-#define G_Reload_Source_Switching _bit15
-#define G_Loading_On_Gate _bit14
-#define G_Gate_Polarity _bit13
-
-#define G_Counting_Once(a) (((a)&0x03)<<10)
-#define G_Stop_Mode(a) (((a)&0x03)<<5)
-#define G_Gate_On_Both_Edges _bit2
-
-/* G_Status_Register */
-#define G1_Gate_Error_St _bit15
-#define G0_Gate_Error_St _bit14
-#define G1_TC_Error_St _bit13
-#define G0_TC_Error_St _bit12
-#define G1_No_Load_Between_Gates_St _bit11
-#define G0_No_Load_Between_Gates_St _bit10
-#define G1_Armed_St _bit9
-#define G0_Armed_St _bit8
-#define G1_Stale_Data_St _bit7
-#define G0_Stale_Data_St _bit6
-#define G1_Next_Load_Source_St _bit5
-#define G0_Next_Load_Source_St _bit4
-#define G1_Counting_St _bit3
-#define G0_Counting_St _bit2
-#define G1_Save_St _bit1
-#define G0_Save_St _bit0
-
-/* general purpose counter timer */
-#define G_Autoincrement(a) ((a)<<0)
-
-/* Additional windowed registers unique to E series */
-
-/* 16 bit registers shadowed from DAQ-STC */
-#define Window_Address 0x00
-#define Window_Data 0x02
-
-#define Configuration_Memory_Clear 82
-#define ADC_FIFO_Clear 83
-#define DAC_FIFO_Clear 84
-
-/* i/o port offsets */
-
-/* 8 bit registers */
-#define XXX_Status 0x01
-enum XXX_Status_Bits {
- PROMOUT = 0x1,
- AI_FIFO_LOWER_NOT_EMPTY = 0x8,
-};
-#define Serial_Command 0x0d
-#define Misc_Command 0x0f
-#define Port_A 0x19
-#define Port_B 0x1b
-#define Port_C 0x1d
-#define Configuration 0x1f
-#define Strobes 0x01
-#define Channel_A_Mode 0x03
-#define Channel_B_Mode 0x05
-#define Channel_C_Mode 0x07
-#define AI_AO_Select 0x09
-enum AI_AO_Select_Bits {
- AI_DMA_Select_Shift = 0,
- AI_DMA_Select_Mask = 0xf,
- AO_DMA_Select_Shift = 4,
- AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift
-};
-#define G0_G1_Select 0x0b
-static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
-{
- if (channel < 4)
- return 1 << channel;
- if (channel == 4)
- return 0x3;
- if (channel == 5)
- return 0x5;
- BUG();
- return 0;
-}
-
-static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index,
- unsigned mite_channel)
-{
- BUG_ON(gpct_index > 1);
- return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 *
- gpct_index);
-}
-
-static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index)
-{
- BUG_ON(gpct_index > 1);
- return 0xf << (4 * gpct_index);
-}
-
-/* 16 bit registers */
-
-#define Configuration_Memory_Low 0x10
-enum Configuration_Memory_Low_Bits {
- AI_DITHER = 0x200,
- AI_LAST_CHANNEL = 0x8000,
-};
-#define Configuration_Memory_High 0x12
-enum Configuration_Memory_High_Bits {
- AI_AC_COUPLE = 0x800,
- AI_DIFFERENTIAL = 0x1000,
- AI_COMMON = 0x2000,
- AI_GROUND = 0x3000,
-};
-static inline unsigned int AI_CONFIG_CHANNEL(unsigned int channel)
-{
- return channel & 0x3f;
-}
-
-#define ADC_FIFO_Data_Register 0x1c
-
-#define AO_Configuration 0x16
-#define AO_Bipolar _bit0
-#define AO_Deglitch _bit1
-#define AO_Ext_Ref _bit2
-#define AO_Ground_Ref _bit3
-#define AO_Channel(x) ((x) << 8)
-
-#define DAC_FIFO_Data 0x1e
-#define DAC0_Direct_Data 0x18
-#define DAC1_Direct_Data 0x1a
-
-/* 611x registers (these boards differ from the e-series) */
-
-#define Magic_611x 0x19 /* w8 (new) */
-#define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
-#define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */
-#define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */
-#define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */
-#define Cal_Gain_Select_611x 0x05 /* w8 (new) */
-
-#define AO_Window_Address_611x 0x18
-#define AO_Window_Data_611x 0x1e
-
-/* 6143 registers */
-#define Magic_6143 0x19 /* w8 */
-#define G0G1_DMA_Select_6143 0x0B /* w8 */
-#define PipelineDelay_6143 0x1f /* w8 */
-#define EOC_Set_6143 0x1D /* w8 */
-#define AIDMA_Select_6143 0x09 /* w8 */
-#define AIFIFO_Data_6143 0x8C /* w32 */
-#define AIFIFO_Flag_6143 0x84 /* w32 */
-#define AIFIFO_Control_6143 0x88 /* w32 */
-#define AIFIFO_Status_6143 0x88 /* w32 */
-#define AIFIFO_DMAThreshold_6143 0x90 /* w32 */
-#define AIFIFO_Words_Available_6143 0x94 /* w32 */
-
-#define Calibration_Channel_6143 0x42 /* w16 */
-#define Calibration_LowTime_6143 0x20 /* w16 */
-#define Calibration_HighTime_6143 0x22 /* w16 */
-#define Relay_Counter_Load_Val__6143 0x4C /* w32 */
-#define Signature_6143 0x50 /* w32 */
-#define Release_Date_6143 0x54 /* w32 */
-#define Release_Oldest_Date_6143 0x58 /* w32 */
-
-#define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */
-#define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */
-#define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */
-#define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */
-#define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */
-#define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */
-#define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */
-#define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */
-
-/* 671x, 611x registers */
-
-/* 671xi, 611x windowed ao registers */
-enum windowed_regs_67xx_61xx {
- AO_Immediate_671x = 0x11, /* W 16 */
- AO_Timed_611x = 0x10, /* W 16 */
- AO_FIFO_Offset_Load_611x = 0x13, /* W32 */
- AO_Later_Single_Point_Updates = 0x14, /* W 16 */
- AO_Waveform_Generation_611x = 0x15, /* W 16 */
- AO_Misc_611x = 0x16, /* W 16 */
- AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */
- AO_Configuration_2_67xx = 0x18, /* W 16 */
- CAL_ADC_Command_67xx = 0x19, /* W 8 */
- CAL_ADC_Status_67xx = 0x1a, /* R 8 */
- CAL_ADC_Data_67xx = 0x1b, /* R 16 */
- CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */
- CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */
-};
-static inline unsigned int DACx_Direct_Data_671x(int channel)
-{
- return channel;
-}
+/*
+ * 611x registers (these boards differ from the e-series)
+ */
+#define NI611X_MAGIC_REG 0x19 /* w8 (new) */
+#define NI611X_CALIB_CHAN_SEL_REG 0x1a /* w16 (new) */
+#define NI611X_AI_FIFO_DATA_REG 0x1c /* r32 (incompatible) */
+#define NI611X_AI_FIFO_OFFSET_LOAD_REG 0x05 /* r8 (new) */
+#define NI611X_AO_FIFO_DATA_REG 0x14 /* w32 (incompatible) */
+#define NI611X_CAL_GAIN_SEL_REG 0x05 /* w8 (new) */
-enum AO_Misc_611x_Bits {
- CLEAR_WG = 1,
-};
-enum cs5529_configuration_bits {
- CSCFG_CAL_CONTROL_MASK = 0x7,
- CSCFG_SELF_CAL_OFFSET = 0x1,
- CSCFG_SELF_CAL_GAIN = 0x2,
- CSCFG_SELF_CAL_OFFSET_GAIN = 0x3,
- CSCFG_SYSTEM_CAL_OFFSET = 0x5,
- CSCFG_SYSTEM_CAL_GAIN = 0x6,
- CSCFG_DONE = 1 << 3,
- CSCFG_POWER_SAVE_SELECT = 1 << 4,
- CSCFG_PORT_MODE = 1 << 5,
- CSCFG_RESET_VALID = 1 << 6,
- CSCFG_RESET = 1 << 7,
- CSCFG_UNIPOLAR = 1 << 12,
- CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13,
- CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13,
- CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13,
- CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13,
- CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13,
- CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13,
- CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13,
- CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13,
- CSCFG_WORD_RATE_MASK = 0x7 << 13,
- CSCFG_LOW_POWER = 1 << 16,
-};
-static inline unsigned int CS5529_CONFIG_DOUT(int output)
-{
- return 1 << (18 + output);
-}
-
-static inline unsigned int CS5529_CONFIG_AOUT(int output)
-{
- return 1 << (22 + output);
-}
-
-enum cs5529_command_bits {
- CSCMD_POWER_SAVE = 0x1,
- CSCMD_REGISTER_SELECT_MASK = 0xe,
- CSCMD_OFFSET_REGISTER = 0x0,
- CSCMD_GAIN_REGISTER = 0x2,
- CSCMD_CONFIG_REGISTER = 0x4,
- CSCMD_READ = 0x10,
- CSCMD_CONTINUOUS_CONVERSIONS = 0x20,
- CSCMD_SINGLE_CONVERSION = 0x40,
- CSCMD_COMMAND = 0x80,
-};
-enum cs5529_status_bits {
- CSS_ADC_BUSY = 0x1,
- CSS_OSC_DETECT = 0x2, /* indicates adc error */
- CSS_OVERRANGE = 0x4,
-};
-#define SerDacLd(x) (0x08<<(x))
+#define NI611X_AO_WINDOW_ADDR_REG 0x18
+#define NI611X_AO_WINDOW_DATA_REG 0x1e
/*
- This is stuff unique to the NI E series drivers,
- but I thought I'd put it here anyway.
-*/
-
-enum { ai_gain_16 =
- 0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x,
- ai_gain_628x, ai_gain_6143
-};
-enum caldac_enum { caldac_none = 0, mb88341, dac8800, dac8043, ad8522,
- ad8804, ad8842, ad8804_debug
-};
-enum ni_reg_type {
- ni_reg_normal = 0x0,
- ni_reg_611x = 0x1,
- ni_reg_6711 = 0x2,
- ni_reg_6713 = 0x4,
- ni_reg_67xx_mask = 0x6,
- ni_reg_6xxx_mask = 0x7,
- ni_reg_622x = 0x8,
- ni_reg_625x = 0x10,
- ni_reg_628x = 0x18,
- ni_reg_m_series_mask = 0x18,
- ni_reg_6143 = 0x20
-};
+ * 6143 registers
+ */
+#define NI6143_MAGIC_REG 0x19 /* w8 */
+#define NI6143_DMA_G0_G1_SEL_REG 0x0b /* w8 */
+#define NI6143_PIPELINE_DELAY_REG 0x1f /* w8 */
+#define NI6143_EOC_SET_REG 0x1d /* w8 */
+#define NI6143_DMA_AI_SEL_REG 0x09 /* w8 */
+#define NI6143_AI_FIFO_DATA_REG 0x8c /* r32 */
+#define NI6143_AI_FIFO_FLAG_REG 0x84 /* w32 */
+#define NI6143_AI_FIFO_CTRL_REG 0x88 /* w32 */
+#define NI6143_AI_FIFO_STATUS_REG 0x88 /* r32 */
+#define NI6143_AI_FIFO_DMA_THRESH_REG 0x90 /* w32 */
+#define NI6143_AI_FIFO_WORDS_AVAIL_REG 0x94 /* w32 */
+
+#define NI6143_CALIB_CHAN_REG 0x42 /* w16 */
+#define NI6143_CALIB_CHAN_RELAY_ON BIT(15)
+#define NI6143_CALIB_CHAN_RELAY_OFF BIT(14)
+#define NI6143_CALIB_CHAN(x) (((x) & 0xf) << 0)
+#define NI6143_CALIB_CHAN_GND_GND NI6143_CALIB_CHAN(0) /* Offset Cal */
+#define NI6143_CALIB_CHAN_2V5_GND NI6143_CALIB_CHAN(2) /* 2.5V ref */
+#define NI6143_CALIB_CHAN_PWM_GND NI6143_CALIB_CHAN(5) /* +-5V Self Cal */
+#define NI6143_CALIB_CHAN_2V5_PWM NI6143_CALIB_CHAN(10) /* PWM Cal */
+#define NI6143_CALIB_CHAN_PWM_PWM NI6143_CALIB_CHAN(13) /* CMRR */
+#define NI6143_CALIB_CHAN_GND_PWM NI6143_CALIB_CHAN(14) /* PWM Cal */
+#define NI6143_CALIB_LO_TIME_REG 0x20 /* w16 */
+#define NI6143_CALIB_HI_TIME_REG 0x22 /* w16 */
+#define NI6143_RELAY_COUNTER_LOAD_REG 0x4c /* w32 */
+#define NI6143_SIGNATURE_REG 0x50 /* w32 */
+#define NI6143_RELEASE_DATE_REG 0x54 /* w32 */
+#define NI6143_RELEASE_OLDEST_DATE_REG 0x58 /* w32 */
-static const struct comedi_lrange range_ni_E_ao_ext;
+/*
+ * 671x, 611x windowed ao registers
+ */
+#define NI671X_DAC_DIRECT_DATA_REG(x) (0x00 + (x)) /* w16 */
+#define NI611X_AO_TIMED_REG 0x10 /* w16 */
+#define NI671X_AO_IMMEDIATE_REG 0x11 /* w16 */
+#define NI611X_AO_FIFO_OFFSET_LOAD_REG 0x13 /* w32 */
+#define NI67XX_AO_SP_UPDATES_REG 0x14 /* w16 */
+#define NI611X_AO_WAVEFORM_GEN_REG 0x15 /* w16 */
+#define NI611X_AO_MISC_REG 0x16 /* w16 */
+#define NI611X_AO_MISC_CLEAR_WG BIT(0)
+#define NI67XX_AO_CAL_CHAN_SEL_REG 0x17 /* w16 */
+#define NI67XX_AO_CFG2_REG 0x18 /* w16 */
+#define NI67XX_CAL_CMD_REG 0x19 /* w16 */
+#define NI67XX_CAL_STATUS_REG 0x1a /* r8 */
+#define NI67XX_CAL_STATUS_BUSY BIT(0)
+#define NI67XX_CAL_STATUS_OSC_DETECT BIT(1)
+#define NI67XX_CAL_STATUS_OVERRANGE BIT(2)
+#define NI67XX_CAL_DATA_REG 0x1b /* r16 */
+#define NI67XX_CAL_CFG_HI_REG 0x1c /* rw16 */
+#define NI67XX_CAL_CFG_LO_REG 0x1d /* rw16 */
+
+#define CS5529_CMD_CB BIT(7)
+#define CS5529_CMD_SINGLE_CONV BIT(6)
+#define CS5529_CMD_CONT_CONV BIT(5)
+#define CS5529_CMD_READ BIT(4)
+#define CS5529_CMD_REG(x) (((x) & 0x7) << 1)
+#define CS5529_CMD_REG_MASK CS5529_CMD_REG(7)
+#define CS5529_CMD_PWR_SAVE BIT(0)
+
+#define CS5529_OFFSET_REG CS5529_CMD_REG(0)
+#define CS5529_GAIN_REG CS5529_CMD_REG(1)
+#define CS5529_CONV_DATA_REG CS5529_CMD_REG(3)
+#define CS5529_SETUP_REG CS5529_CMD_REG(4)
+
+#define CS5529_CFG_REG CS5529_CMD_REG(2)
+#define CS5529_CFG_AOUT(x) BIT(22 + (x))
+#define CS5529_CFG_DOUT(x) BIT(18 + (x))
+#define CS5529_CFG_LOW_PWR_MODE BIT(16)
+#define CS5529_CFG_WORD_RATE(x) (((x) & 0x7) << 13)
+#define CS5529_CFG_WORD_RATE_MASK CS5529_CFG_WORD_RATE(0x7)
+#define CS5529_CFG_WORD_RATE_2180 CS5529_CFG_WORD_RATE(0)
+#define CS5529_CFG_WORD_RATE_1092 CS5529_CFG_WORD_RATE(1)
+#define CS5529_CFG_WORD_RATE_532 CS5529_CFG_WORD_RATE(2)
+#define CS5529_CFG_WORD_RATE_388 CS5529_CFG_WORD_RATE(3)
+#define CS5529_CFG_WORD_RATE_324 CS5529_CFG_WORD_RATE(4)
+#define CS5529_CFG_WORD_RATE_17444 CS5529_CFG_WORD_RATE(5)
+#define CS5529_CFG_WORD_RATE_8724 CS5529_CFG_WORD_RATE(6)
+#define CS5529_CFG_WORD_RATE_4364 CS5529_CFG_WORD_RATE(7)
+#define CS5529_CFG_UNIPOLAR BIT(12)
+#define CS5529_CFG_RESET BIT(7)
+#define CS5529_CFG_RESET_VALID BIT(6)
+#define CS5529_CFG_PORT_FLAG BIT(5)
+#define CS5529_CFG_PWR_SAVE_SEL BIT(4)
+#define CS5529_CFG_DONE_FLAG BIT(3)
+#define CS5529_CFG_CALIB(x) (((x) & 0x7) << 0)
+#define CS5529_CFG_CALIB_NONE CS5529_CFG_CALIB(0)
+#define CS5529_CFG_CALIB_OFFSET_SELF CS5529_CFG_CALIB(1)
+#define CS5529_CFG_CALIB_GAIN_SELF CS5529_CFG_CALIB(2)
+#define CS5529_CFG_CALIB_BOTH_SELF CS5529_CFG_CALIB(3)
+#define CS5529_CFG_CALIB_OFFSET_SYS CS5529_CFG_CALIB(5)
+#define CS5529_CFG_CALIB_GAIN_SYS CS5529_CFG_CALIB(6)
/*
* M-Series specific registers not handled by the DAQ-STC and GPCT register
#define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
#define NI_M_AO_REF_ATTENUATION_X5 BIT(0)
-#define M_SERIES_EEPROM_SIZE 1024
+enum {
+ ai_gain_16 = 0,
+ ai_gain_8,
+ ai_gain_14,
+ ai_gain_4,
+ ai_gain_611x,
+ ai_gain_622x,
+ ai_gain_628x,
+ ai_gain_6143
+};
+
+enum caldac_enum {
+ caldac_none = 0,
+ mb88341,
+ dac8800,
+ dac8043,
+ ad8522,
+ ad8804,
+ ad8842,
+ ad8804_debug
+};
+
+enum ni_reg_type {
+ ni_reg_normal = 0x0,
+ ni_reg_611x = 0x1,
+ ni_reg_6711 = 0x2,
+ ni_reg_6713 = 0x4,
+ ni_reg_67xx_mask = 0x6,
+ ni_reg_6xxx_mask = 0x7,
+ ni_reg_622x = 0x8,
+ ni_reg_625x = 0x10,
+ ni_reg_628x = 0x18,
+ ni_reg_m_series_mask = 0x18,
+ ni_reg_6143 = 0x20
+};
struct ni_board_struct {
const char *name;
enum caldac_enum caldac[3];
};
-#define MAX_N_CALDACS 34
-#define MAX_N_AO_CHAN 8
-#define NUM_GPCT 2
+#define MAX_N_CALDACS 34
+#define MAX_N_AO_CHAN 8
+#define NUM_GPCT 2
+
+#define NUM_PFI_OUTPUT_SELECT_REGS 6
+
+#define M_SERIES_EEPROM_SIZE 1024
struct ni_private {
unsigned short dio_output;
int aimode;
unsigned int ai_calib_source;
unsigned int ai_calib_source_enabled;
+ /* protects access to windowed registers */
spinlock_t window_lock;
+ /* protects interrupt/dma register access */
spinlock_t soft_reg_copy_lock;
+ /* protects mite DMA channel request/release */
spinlock_t mite_channel_lock;
int changain_state;
unsigned int is_6713:1;
};
+static const struct comedi_lrange range_ni_E_ao_ext;
+
#endif /* _COMEDI_NI_STC_H */
projects / firefly-linux-kernel-4.4.55.git / blobdiff