Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

[firefly-linux-kernel-4.4.55.git] / drivers / thermal / samsung / exynos_tmu_data.h

diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index f0979e598491cc80f3bd0c3782090b06b172e223..63de598c9c2c3f9b8804110f086ed384991f547a 100644 (file)
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -39,55 +39,31 @@
 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
 #define EXYNOS_TMU_CORE_EN_SHIFT       0
 
+/* Exynos3250 specific registers */
+#define EXYNOS_TMU_TRIMINFO_CON1       0x10
+
 /* Exynos4210 specific registers */
 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP      0x44
 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
-#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
-#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
-#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
-#define EXYNOS4210_TMU_REG_PAST_TEMP0  0x60
-#define EXYNOS4210_TMU_REG_PAST_TEMP1  0x64
-#define EXYNOS4210_TMU_REG_PAST_TEMP2  0x68
-#define EXYNOS4210_TMU_REG_PAST_TEMP3  0x6C
-
-#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK        0x1
-#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK        0x10
-#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK        0x100
-#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK        0x1000
-#define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
-#define EXYNOS4210_TMU_INTCLEAR_VAL    0x1111
-
-/* Exynos5250 and Exynos4412 specific registers */
-#define EXYNOS_TMU_TRIMINFO_CON        0x14
+
+/* Exynos5250, Exynos4412, Exynos3250 specific registers */
+#define EXYNOS_TMU_TRIMINFO_CON2       0x14
 #define EXYNOS_THD_TEMP_RISE           0x50
 #define EXYNOS_THD_TEMP_FALL           0x54
 #define EXYNOS_EMUL_CON                0x80
 
-#define EXYNOS_TRIMINFO_RELOAD_SHIFT   1
+#define EXYNOS_TRIMINFO_RELOAD_ENABLE  1
 #define EXYNOS_TRIMINFO_25_SHIFT       0
 #define EXYNOS_TRIMINFO_85_SHIFT       8
-#define EXYNOS_TMU_RISE_INT_MASK       0x111
-#define EXYNOS_TMU_RISE_INT_SHIFT      0
-#define EXYNOS_TMU_FALL_INT_MASK       0x111
-#define EXYNOS_TMU_CLEAR_RISE_INT      0x111
-#define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 12)
-#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT        12
-#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT    16
-#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT    4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
 #define EXYNOS_TMU_TRIP_MODE_MASK      0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
-#define EXYNOS_TMU_CALIB_MODE_SHIFT    4
-#define EXYNOS_TMU_CALIB_MODE_MASK     0x3
 
 #define EXYNOS_TMU_INTEN_RISE0_SHIFT   0
 #define EXYNOS_TMU_INTEN_RISE1_SHIFT   4
 #define EXYNOS_TMU_INTEN_RISE2_SHIFT   8
 #define EXYNOS_TMU_INTEN_RISE3_SHIFT   12
 #define EXYNOS_TMU_INTEN_FALL0_SHIFT   16
-#define EXYNOS_TMU_INTEN_FALL1_SHIFT   20
-#define EXYNOS_TMU_INTEN_FALL2_SHIFT   24
-#define EXYNOS_TMU_INTEN_FALL3_SHIFT   28
 
 #define EXYNOS_EMUL_TIME       0x57F0
 #define EXYNOS_EMUL_TIME_MASK  0xffff
@@ -99,14 +75,9 @@
 #define EXYNOS_MAX_TRIGGER_PER_REG     4
 
 /* Exynos5260 specific */
-#define EXYNOS_TMU_REG_CONTROL1                        0x24
 #define EXYNOS5260_TMU_REG_INTEN               0xC0
 #define EXYNOS5260_TMU_REG_INTSTAT             0xC4
 #define EXYNOS5260_TMU_REG_INTCLEAR            0xC8
-#define EXYNOS5260_TMU_CLEAR_RISE_INT          0x1111
-#define EXYNOS5260_TMU_CLEAR_FALL_INT          (0x1111 << 16)
-#define EXYNOS5260_TMU_RISE_INT_MASK           0x1111
-#define EXYNOS5260_TMU_FALL_INT_MASK           0x1111
 #define EXYNOS5260_EMUL_CON                    0x100
 
 /* Exynos4412 specific */
@@ -122,29 +93,17 @@
 #define EXYNOS5440_TMU_S0_7_TH0                        0x110
 #define EXYNOS5440_TMU_S0_7_TH1                        0x130
 #define EXYNOS5440_TMU_S0_7_TH2                        0x150
-#define EXYNOS5440_TMU_S0_7_EVTEN              0x1F0
 #define EXYNOS5440_TMU_S0_7_IRQEN              0x210
 #define EXYNOS5440_TMU_S0_7_IRQ                        0x230
 /* exynos5440 common registers */
 #define EXYNOS5440_TMU_IRQ_STATUS              0x000
 #define EXYNOS5440_TMU_PMIN                    0x004
-#define EXYNOS5440_TMU_TEMP                    0x008
 
-#define EXYNOS5440_TMU_RISE_INT_MASK           0xf
-#define EXYNOS5440_TMU_RISE_INT_SHIFT          0
-#define EXYNOS5440_TMU_FALL_INT_MASK           0xf
 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT       0
 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT       1
 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT       2
 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT       3
 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT       4
-#define EXYNOS5440_TMU_INTEN_FALL1_SHIFT       5
-#define EXYNOS5440_TMU_INTEN_FALL2_SHIFT       6
-#define EXYNOS5440_TMU_INTEN_FALL3_SHIFT       7
-#define EXYNOS5440_TMU_TH_RISE0_SHIFT          0
-#define EXYNOS5440_TMU_TH_RISE1_SHIFT          8
-#define EXYNOS5440_TMU_TH_RISE2_SHIFT          16
-#define EXYNOS5440_TMU_TH_RISE3_SHIFT          24
 #define EXYNOS5440_TMU_TH_RISE4_SHIFT          24
 #define EXYNOS5440_EFUSE_SWAP_OFFSET           8