#endif
#ifdef DWC_UTE_PER_IO
-extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
+extern void complete_xiso_ep(dwc_otg_pcd_ep_t *ep);
#endif
-//#define PRINT_CFI_DMA_DESCS
+/* #define PRINT_CFI_DMA_DESCS */
#define DEBUG_EP0
/**
* This function updates OTG.
*/
-static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
+static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *pcd, const unsigned reset)
{
if (reset) {
/**
* This function prints the ep0 state for debug purposes.
*/
-static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
+static inline void print_ep0_state(dwc_otg_pcd_t *pcd)
{
#ifdef DEBUG
char str[40];
}
/**
- * This function calculate the size of the payload in the memory
- * for out endpoints and prints size for debug purposes(used in
+ * This function calculate the size of the payload in the memory
+ * for out endpoints and prints size for debug purposes(used in
* 2.93a DevOutNak feature).
*/
-static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep)
+static inline void print_memory_payload(dwc_otg_pcd_t *pcd, dwc_ep_t *ep)
{
#ifdef DEBUG
deptsiz_data_t deptsiz_init = {.d32 = 0 };
deptsiz_data_t deptsiz_updt = {.d32 = 0 };
int pack_num;
unsigned payload;
-
+
deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
deptsiz_updt.d32 =
- DWC_READ_REG32(&pcd->core_if->dev_if->
- out_ep_regs[ep->num]->doeptsiz);
+ DWC_READ_REG32(&pcd->core_if->dev_if->
+ out_ep_regs[ep->num]->doeptsiz);
/* Payload will be */
payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
/* Packet count is decremented every time a packet
* is written to the RxFIFO not in to the external memory
* So, if payload == 0, then it means no packet was sent to ext memory*/
- pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
- DWC_DEBUGPL(DBG_PCDV,
- "Payload for EP%d-%s\n",
- ep->num, (ep->is_in ? "IN" : "OUT"));
- DWC_DEBUGPL(DBG_PCDV,
- "Number of transfered bytes = 0x%08x\n", payload);
- DWC_DEBUGPL(DBG_PCDV,
- "Number of transfered packets = %d\n", pack_num);
-#endif
+ pack_num =
+ (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
+ DWC_DEBUGPL(DBG_PCDV, "Payload for EP%d-%s\n", ep->num,
+ (ep->is_in ? "IN" : "OUT"));
+ DWC_DEBUGPL(DBG_PCDV, "Number of transfered bytes = 0x%08x\n", payload);
+ DWC_DEBUGPL(DBG_PCDV, "Number of transfered packets = %d\n", pack_num);
+#endif
}
-
#ifdef DWC_UTE_CFI
static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
- const uint8_t * epname, int descnum)
+ const uint8_t *epname, int descnum)
{
CFI_INFO
("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
/**
* This function returns pointer to in ep struct with number ep_num
*/
-static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
+static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
{
int i;
int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
/**
* This function returns pointer to out ep struct with number ep_num
*/
-static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
+static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
{
int i;
int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
* This functions gets a pointer to an EP from the wIndex address
* value of the control request.
*/
-dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
+dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t *pcd, u16 wIndex)
{
dwc_otg_pcd_ep_t *ep;
uint32_t ep_num = UE_GET_ADDR(wIndex);
* This function checks the EP request queue, if the queue is not
* empty the next request is started.
*/
-void start_next_request(dwc_otg_pcd_ep_t * ep)
+void start_next_request(dwc_otg_pcd_ep_t *ep)
{
dwc_otg_pcd_request_t *req = 0;
uint32_t max_transfer =
* This function handles the SOF Interrupts. At this time the SOF
* Interrupt is disabled.
*/
-int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
* -# If OUT Data Packet call dwc_otg_read_packet to copy the data
* to the destination buffer
*/
-int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
#endif
- //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
+ /* DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); */
/* Disable the Rx Status Queue Level interrupt */
gintmask.b.rxstsqlvl = 1;
DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
gintsts.b.rxstsqlvl = 1;
DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
- //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
+ /* DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); */
return 1;
}
* @param core_if Programming view of DWC_otg controller.
*
*/
-static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
+static inline int get_ep_of_last_in_token(dwc_otg_core_if_t *core_if)
{
dwc_otg_device_global_regs_t *dev_global_regs =
core_if->dev_if->dev_global_regs;
volatile uint32_t *addr = &dev_global_regs->dtknqr1;
int epnum = 0;
- //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
+ /* DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); */
/* Read the DTKNQ Registers */
for (i = 0; i < DTKNQ_REG_CNT; i++) {
in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
ndx = dtknqr1.b.intknwptr - 1;
- //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
+ /* DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx); */
if (ndx == -1) {
/** @todo Find a simpler way to calculate the max
* queue position.*/
epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
}
}
- //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
+ /* DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum); */
return epnum;
}
* The active request is checked for the next packet to be loaded into
* the non-periodic Tx FIFO.
*/
-int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
* The active request is checked for the next packet to be loaded into
* apropriate Tx FIFO.
*/
-static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
+static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
* any active requests and informs the Gadget driver of the
* disconnect.
*/
-void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
+void dwc_otg_pcd_stop(dwc_otg_pcd_t *pcd)
{
int i, num_in_eps, num_out_eps;
dwc_otg_pcd_ep_t *ep;
/**
* This interrupt indicates that ...
*/
-int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t *pcd)
{
gintmsk_data_t intr_mask = {.d32 = 0 };
gintsts_data_t gintsts;
/**
* This interrupt indicates that ...
*/
-int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t *pcd)
{
gintsts_data_t gintsts;
#if defined(VERBOSE)
* @param core_if Programming view of DWC_otg controller.
* @param pcd Programming view of the PCD.
*/
-static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
- dwc_otg_pcd_t * pcd)
+static inline void ep0_out_start(dwc_otg_core_if_t *core_if,
+ dwc_otg_pcd_t *pcd)
{
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
deptsiz0_data_t doeptsize0 = {.d32 = 0 };
}
}
- doeptsize0.b.supcnt = 3;
+ doeptsize0.b.supcnt = 1;
doeptsize0.b.pktcnt = 1;
doeptsize0.b.xfersize = 8 * 3;
doepctl.b.cnak = 1;
DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
} else {
- DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
+ DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0,
+ doepctl.d32);
}
#ifdef VERBOSE
* At this point, all the required initialization, except for enabling
* the control 0 OUT endpoint is done, for receiving SETUP packets.
*/
-int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
core_if->lx_state = DWC_OTG_L0;
core_if->otg_sts = 0;
-
+
DWC_PRINTF("USB RESET\n");
#ifdef DWC_EN_ISOC
for (i = 1; i < 16; ++i) {
if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
core_if->start_predict = 0;
for (i = 0; i <= core_if->dev_if->num_in_eps; ++i) {
- core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
+ core_if->nextep_seq[i] = 0xff; /*0xff - EP not active */
}
core_if->nextep_seq[0] = 0;
core_if->first_in_nextep_seq = 0;
}
if (core_if->dma_desc_enable)
doepmsk.b.bna = 1;
-/*
+/*
doepmsk.b.babble = 1;
doepmsk.b.nyet = 1;
-
+
if (core_if->dma_enable) {
doepmsk.b.nak = 1;
}
diepmsk.b.bna = 1;
}
*/
-/*
+/*
if (core_if->dma_enable) {
diepmsk.b.nak = 1;
}
*
* @param core_if Programming view of DWC_otg controller.
*/
-static int get_device_speed(dwc_otg_core_if_t * core_if)
+static int get_device_speed(dwc_otg_core_if_t *core_if)
{
dsts_data_t dsts;
int speed = 0;
* data structure.
* Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
*/
-int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t *pcd)
{
dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
- utmi16b = 5; //vahrama old value was 6;
+ utmi16b = 5; /* vahrama old value was 6; */
utmi8b = 9;
} else {
utmi16b = 4;
if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
ep0_out_start(GET_CORE_IF(pcd), pcd);
}
-
#ifdef DEBUG_EP0
print_ep0_state(pcd);
#endif
* Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
* read all the data from the Rx FIFO.
*/
-int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t *pcd)
{
gintmsk_data_t intr_mask = {.d32 = 0 };
gintsts_data_t gintsts;
* for periodic transactions. If there is a periodic transaction for
* the next frame, load the packets into the EP periodic Tx FIFO.
*/
-int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t *pcd)
{
gintmsk_data_t intr_mask = {.d32 = 0 };
gintsts_data_t gintsts;
* is flushed, so it can be reloaded in the order seen in the IN Token
* Queue.
*/
-int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t *pcd)
{
gintsts_data_t gintsts;
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
core_if->start_predict = 1;
DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
-
- gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+
+ gintsts.d32 =
+ DWC_READ_REG32(&core_if->core_global_regs->gintsts);
if (!gintsts.b.ginnakeff) {
/* Disable EP Mismatch interrupt */
intr_mask.d32 = 0;
intr_mask.b.epmismatch = 1;
- DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
+ intr_mask.d32, 0);
/* Enable the Global IN NAK Effective Interrupt */
intr_mask.d32 = 0;
intr_mask.b.ginnakeff = 1;
- DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
+ intr_mask.d32);
/* Set the global non-periodic IN NAK handshake */
- dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
+ dctl.d32 =
+ DWC_READ_REG32(&core_if->dev_if->
+ dev_global_regs->dctl);
dctl.b.sgnpinnak = 1;
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
+ dctl.d32);
} else {
- DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
+ DWC_PRINTF
+ ("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
}
/* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
* handler after Global IN NAK Effective interrupt will be asserted */
* core has stopped fetching data for IN endpoints due to the unavailability of
* TxFIFO space or Request Queue space. This interrupt is used by the
* application for an endpoint mismatch algorithm.
- *
- * @param pcd The PCD
+ *
+ * @param pcd The PCD
*/
-int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t *pcd)
{
gintsts_data_t gintsts;
gintmsk_data_t gintmsk_data;
/* Clear the global non-periodic IN NAK handshake */
dctl.d32 = 0;
dctl.b.cgnpinnak = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-
+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,
+ dctl.d32);
+
/* Mask GINTSTS.FETSUSP interrupt */
gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
gintmsk_data.b.fetsusp = 0;
/**
* This funcion stalls EP0.
*/
-static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
+static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val)
{
dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
usb_device_request_t *ctrl = &pcd->setup_pkt->req;
/**
* This functions delegates the setup command to the gadget driver.
*/
-static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
- usb_device_request_t * ctrl)
+static inline void do_gadget_setup(dwc_otg_pcd_t *pcd,
+ usb_device_request_t *ctrl)
{
int ret = 0;
DWC_SPINUNLOCK(pcd->lock);
ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
- if(spin_is_locked((spinlock_t *)pcd->lock))
- DWC_WARN("%s warning: pcd->lock locked without unlock\n", __func__);
+ if (spin_is_locked((spinlock_t *) pcd->lock))
+ DWC_WARN("%s warning: pcd->lock locked without unlock\n",
+ __func__);
DWC_SPINLOCK(pcd->lock);
if (ret < 0) {
ep0_do_stall(pcd, ret);
* This functions delegates the CFI setup commands to the gadget driver.
* This function will return a negative value to indicate a failure.
*/
-static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
+static inline int cfi_gadget_setup(dwc_otg_pcd_t *pcd,
struct cfi_usb_ctrlrequest *ctrl_req)
{
int ret = 0;
* This function starts the Zero-Length Packet for the IN status phase
* of a 2 stage control transfer.
*/
-static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
+static inline void do_setup_in_status_phase(dwc_otg_pcd_t *pcd)
{
dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
if (pcd->ep0state == EP0_STALL) {
dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
/* Prepare for more SETUP Packets */
- //ep0_out_start(GET_CORE_IF(pcd), pcd);
+ /* ep0_out_start(GET_CORE_IF(pcd), pcd); */
}
/**
* This function starts the Zero-Length Packet for the OUT status phase
* of a 2 stage control transfer.
*/
-static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
+static inline void do_setup_out_status_phase(dwc_otg_pcd_t *pcd)
{
dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
if (pcd->ep0state == EP0_STALL) {
* Clear the EP halt (STALL) and if pending requests start the
* transfer.
*/
-static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
+static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
{
if (ep->dwc_ep.stall_clear_flag) {
/* Start Control Status Phase */
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
int test_mode = pcd->test_mode;
-// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
+ /* DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); */
dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
switch (test_mode) {
- case 1: // TEST_J
+ case 1: /* TEST_J */
dctl.b.tstctl = 1;
break;
- case 2: // TEST_K
+ case 2: /* TEST_K */
dctl.b.tstctl = 2;
break;
- case 3: // TEST_SE0_NAK
+ case 3: /* TEST_SE0_NAK */
dctl.b.tstctl = 3;
break;
- case 4: // TEST_PACKET
+ case 4: /* TEST_PACKET */
dctl.b.tstctl = 4;
break;
- case 5: // TEST_FORCE_ENABLE
+ case 5: /* TEST_FORCE_ENABLE */
dctl.b.tstctl = 5;
break;
- case 7:
+ case 7:
dwc_otg_set_hnpreq(core_if, 1);
}
- DWC_PRINTF("test mode = %d\n",test_mode);
+ DWC_PRINTF("test mode = %d\n", test_mode);
core_if->test_mode = test_mode;
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
}
/**
* This function process the GET_STATUS Setup Commands.
*/
-static inline void do_get_status(dwc_otg_pcd_t * pcd)
+static inline void do_get_status(dwc_otg_pcd_t *pcd)
{
usb_device_request_t ctrl = pcd->setup_pkt->req;
dwc_otg_pcd_ep_t *ep;
/**
* This function process the SET_FEATURE Setup Commands.
*/
-static inline void do_set_feature(dwc_otg_pcd_t * pcd)
+static inline void do_set_feature(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
gotgctl.b.devhnpen = 1;
if (core_if->otg_ver == 1)
- DWC_MODIFY_REG32(&global_regs->gotgctl, 0, gotgctl.d32);
+ DWC_MODIFY_REG32(&global_regs->gotgctl,
+ 0, gotgctl.d32);
else {
pcd->b_hnp_enable = 1;
dwc_otg_pcd_update_otg(pcd, 0);
/**@todo Is the gotgctl.devhnpen cleared
* by a USB Reset? */
gotgctl.b.hnpreq = 1;
- DWC_WRITE_REG32(&global_regs->gotgctl, gotgctl.d32);
+ DWC_WRITE_REG32(&global_regs->gotgctl,
+ gotgctl.d32);
}
} else {
ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
/**
* This function process the CLEAR_FEATURE Setup Commands.
*/
-static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
+static inline void do_clear_feature(dwc_otg_pcd_t *pcd)
{
usb_device_request_t ctrl = pcd->setup_pkt->req;
dwc_otg_pcd_ep_t *ep = 0;
/**
* This function process the SET_ADDRESS Setup Commands.
*/
-static inline void do_set_address(dwc_otg_pcd_t * pcd)
+static inline void do_set_address(dwc_otg_pcd_t *pcd)
{
dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
usb_device_request_t ctrl = pcd->setup_pkt->req;
dcfg_data_t dcfg = {.d32 = 0 };
#ifdef DEBUG_EP0
-// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
+ /* DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); */
#endif
dcfg.b.devaddr = UGETW(ctrl.wValue);
DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
*
* When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
* processed by pcd_setup. Calling the Function Driver's setup function from
- * pcd_setup processes the gadget SETUP commands.
+ *pcd_setup processes the gadget SETUP commands.
*/
-static inline void pcd_setup(dwc_otg_pcd_t * pcd)
+static inline void pcd_setup(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
- /** In BDMA more then 1 setup packet is not supported till 3.00a */
- if (core_if->dma_enable && core_if->dma_desc_enable == 0
- && (doeptsize0.b.supcnt < 2)
- && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
- DWC_ERROR
- ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
- }
- if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
- && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
- ctrl =
- (pcd->setup_pkt +
- (3 - doeptsize0.b.supcnt - 1 +
- ep0->dwc_ep.stp_rollover))->req;
- }
#ifdef DEBUG_EP0
DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
ctrl.bmRequestType, ctrl.bRequest,
#ifdef DWC_UTE_CFI
DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
- //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
- ctrl.bRequestType, ctrl.bRequest);
+ /* printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
+ * ctrl.bRequestType, ctrl.bRequest); */
if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
retval = cfi_setup(pcd, &cfi_req);
/** @todo NGS: Handle bad setup packet? */
-///////////////////////////////////////////
-//// --- Standard Request handling --- ////
+ /* --- Standard Request handling --- */
switch (ctrl.bRequest) {
case UR_GET_STATUS:
case UR_SET_INTERFACE:
case UR_SET_CONFIG:
-// _pcd->request_config = 1; /* Configuration changed */
+ /* _pcd->request_config = 1; */ /* Configuration changed */
do_gadget_setup(pcd, &ctrl);
break;
/**
* This function completes the ep0 control transfer.
*/
-static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
+static int32_t ep0_complete_request(dwc_otg_pcd_ep_t *ep)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
&& ctrlreq->bRequest < 0xBF) {
/* Return if the PCD failed to handle the request */
- if ((retval =
- pcd->cfi->ops.
- ctrl_write_complete(pcd->cfi,
- pcd)) < 0) {
+ retval = pcd->cfi->ops.
+ ctrl_write_complete(pcd->cfi, pcd);
+ if (retval < 0) {
CFI_INFO
("ERROR setting a new value in the PCD(%d)\n",
retval);
/* If the gadget needs to be notified on the request */
if (pcd->cfi->need_gadget_att == 1) {
- //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
+ /* retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req); */
retval =
cfi_gadget_setup(pcd,
&pcd->cfi->
#endif
req->sent_zlp = 0;
}
- /* For older cores do setup in status phase in Slave/BDMA modes,
- * starting from 3.00 do that only in slave, and for DMA modes
+ /* For older cores do setup in status phase in Slave/BDMA modes,
+ * starting from 3.00 do that only in slave, and for DMA modes
* just re-enable ep 0 OUT here*/
- if (core_if->dma_enable == 0
- || (core_if->dma_desc_enable == 0
- && core_if->snpsid <= OTG_CORE_REV_2_94a)) {
- do_setup_in_status_phase(pcd);
- } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
- DWC_DEBUGPL(DBG_PCDV,
- "Enable out ep before in status phase\n");
- ep0_out_start(core_if, pcd);
- }
+ do_setup_in_status_phase(pcd);
}
/* Complete the request */
*
* @return The total bytes left to transfered, or a negative value as failure
*/
-static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
+static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t *ep)
{
int32_t ret = 0;
int i;
* This function completes the request for the EP. If there are
* additional requests for the EP in the queue they will be started.
*/
-static void complete_ep(dwc_otg_pcd_ep_t * ep)
+static void complete_ep(dwc_otg_pcd_ep_t *ep)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
DWC_DEBUGPL(DBG_PCDV,
"%d-%s len=%d xfersize=%d pktcnt=%d\n",
ep->dwc_ep.num,
- (ep->dwc_ep.
- is_in ? "IN" : "OUT"),
+ (ep->dwc_ep.is_in ? "IN" :
+ "OUT"),
ep->dwc_ep.xfer_len,
deptsiz.b.xfersize,
deptsiz.b.pktcnt);
dwc_otg_ep_start_transfer
(core_if, &ep->dwc_ep);
} else if (ep->dwc_ep.sent_zlp) {
- /*
+ /*
* This fragment of code should initiate 0
* length transfer in case if it is queued
* a transfer with size divisible to EPs max
if (ep->dwc_ep.type ==
DWC_OTG_EP_TYPE_ISOC) {
req->actual = 0;
- dwc_otg_request_done(ep, req, 0);
+ dwc_otg_request_done(ep, req,
+ 0);
ep->dwc_ep.start_xfer_buff = 0;
ep->dwc_ep.xfer_buff = 0;
start_next_request(ep);
} else
DWC_WARN
- ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
- ep->dwc_ep.num,
- (ep->dwc_ep.is_in ? "IN" : "OUT"),
- deptsiz.b.xfersize,
- deptsiz.b.pktcnt);
+ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
+ ep->dwc_ep.num,
+ (ep->
+ dwc_ep.is_in ? "IN" :
+ "OUT"),
+ deptsiz.b.xfersize,
+ deptsiz.b.pktcnt);
}
} else {
dma_desc = ep->dwc_ep.desc_addr;
deptsiz.b.xfersize,
deptsiz.b.pktcnt);
- /* Check if the whole transfer was completed,
+ /* Check if the whole transfer was completed,
* if no, setup transfer for next portion of data
*/
if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
dwc_otg_ep_start_transfer(core_if,
&ep->dwc_ep);
} else if (ep->dwc_ep.sent_zlp) {
- /*
+ /*
* This fragment of code should initiate 0
* length trasfer in case if it is queued
* a trasfer with size divisible to EPs max
#ifdef DWC_UTE_CFI
}
#endif
- /* Checking for interrupt Out transfers with not
- * dword aligned mps sizes
+ /* Checking for interrupt Out transfers with not
+ * dword aligned mps sizes
*/
if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
(ep->dwc_ep.maxpacket % 4)) {
MAX_DMA_DESC_CNT))
ep->dwc_ep.xfer_len -=
(ep->dwc_ep.desc_cnt -
- 1) * ep->dwc_ep.maxpacket +
+ 1)*ep->dwc_ep.maxpacket +
ep->dwc_ep.xfer_len %
ep->dwc_ep.maxpacket;
else
ep->dwc_ep.dma_addr += byte_count;
ep->dwc_ep.xfer_count += byte_count;
- /* Check if the whole transfer was completed,
+ /* Check if the whole transfer was completed,
* if no, setup transfer for next portion of data
*/
if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
dwc_otg_ep_start_transfer(core_if,
&ep->dwc_ep);
} else if (ep->dwc_ep.sent_zlp) {
- /*
+ /*
* This fragment of code should initiate 0
* length trasfer in case if it is queued
* a trasfer with size divisible to EPs max
}
}
} else {
- /* Check if the whole transfer was completed,
+ /* Check if the whole transfer was completed,
* if no, setup transfer for next portion of data
*/
if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
} else if (ep->dwc_ep.sent_zlp) {
- /*
+ /*
* This fragment of code should initiate 0
* length transfer in case if it is queued
* a transfer with size divisible to EPs max
#endif
if (req->dw_align_buf) {
if (!ep->dwc_ep.is_in) {
- dwc_memcpy(req->buf, req->dw_align_buf, req->length);
+ dwc_memcpy(req->buf, req->dw_align_buf,
+ req->length);
}
DWC_DMA_FREE(req->length, req->dw_align_buf,
req->dw_align_buf_dma);
* This function BNA interrupt for Isochronous EPs
*
*/
-static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
+static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t *ep)
{
dwc_ep_t *dwc_ep = &ep->dwc_ep;
volatile uint32_t *addr;
- depctl_data_t depctl = {.d32 = 0 };
+ depctl_data_t depctl = {
+ .d32 = 0};
dwc_otg_pcd_t *pcd = ep->pcd;
dwc_otg_dev_dma_desc_t *dma_desc;
int i;
dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
if (dwc_ep->is_in) {
- dev_dma_desc_sts_t sts = {.d32 = 0 };
+ dev_dma_desc_sts_t sts = {
+ .d32 = 0};
for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
sts.d32 = dma_desc->status.d32;
sts.b_iso_in.bs = BS_HOST_READY;
dma_desc->status.d32 = sts.d32;
}
} else {
- dev_dma_desc_sts_t sts = {.d32 = 0 };
+ dev_dma_desc_sts_t sts = {
+ .d32 = 0};
for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
sts.d32 = dma_desc->status.d32;
sts.b_iso_out.bs = BS_HOST_READY;
* @param ep The EP to start the transfer on.
*
*/
-void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+void set_current_pkt_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
- deptsiz_data_t deptsiz = {.d32 = 0 };
+ deptsiz_data_t deptsiz = {
+ .d32 = 0};
dma_addr_t dma_addr;
uint32_t offset;
* @param dwc_ep The EP to start the transfer on.
*
*/
-static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
- dwc_ep_t * dwc_ep)
-{
+static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if,
+ dwc_ep_t *dwc_ep) {
dwc_otg_dev_dma_desc_t *dma_desc;
- dev_dma_desc_sts_t sts = {.d32 = 0 };
+ dev_dma_desc_sts_t sts = {
+ .d32 = 0};
iso_pkt_info_t *iso_packet;
uint32_t data_per_desc;
uint32_t offset;
if (dwc_ep->is_in == 0) {
dma_desc =
dwc_ep->iso_desc_addr +
- dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+ dwc_ep->desc_cnt*dwc_ep->proc_buf_num;
offset = 0;
for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
i += dwc_ep->pkt_per_frm) {
for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
data_per_desc =
- ((j + 1) * dwc_ep->maxpacket >
+ ((j + 1)*dwc_ep->maxpacket >
dwc_ep->
data_per_frame) ? dwc_ep->data_per_frame -
- j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+ j*dwc_ep->maxpacket : dwc_ep->maxpacket;
data_per_desc +=
(data_per_desc % 4) ? (4 -
data_per_desc %
for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
data_per_desc =
- ((j + 1) * dwc_ep->maxpacket >
+ ((j + 1)*dwc_ep->maxpacket >
dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
- j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+ j*dwc_ep->maxpacket : dwc_ep->maxpacket;
data_per_desc +=
(data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
dma_desc =
dwc_ep->iso_desc_addr +
- dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+ dwc_ep->desc_cnt*dwc_ep->proc_buf_num;
for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
sts.d32 = dma_desc->status.d32;
* @param dwc_ep The EP to start the transfer on.
*
*/
-static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
+static void reinit_ddma_iso_xfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
{
int i, j;
dwc_otg_dev_dma_desc_t *dma_desc;
dma_addr_t dma_ad;
volatile uint32_t *addr;
- dev_dma_desc_sts_t sts = {.d32 = 0 };
+ dev_dma_desc_sts_t sts = {
+ .d32 = 0};
uint32_t data_per_desc;
if (dwc_ep->is_in == 0) {
if (dwc_ep->is_in == 0) {
dma_desc =
dwc_ep->iso_desc_addr +
- dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+ dwc_ep->desc_cnt*dwc_ep->proc_buf_num;
sts.b_iso_out.bs = BS_HOST_READY;
sts.b_iso_out.rxsts = 0;
i += dwc_ep->pkt_per_frm) {
for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
data_per_desc =
- ((j + 1) * dwc_ep->maxpacket >
+ ((j + 1)*dwc_ep->maxpacket >
dwc_ep->
data_per_frame) ? dwc_ep->data_per_frame -
- j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+ j*dwc_ep->maxpacket : dwc_ep->maxpacket;
data_per_desc +=
(data_per_desc % 4) ? (4 -
data_per_desc %
for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
data_per_desc =
- ((j + 1) * dwc_ep->maxpacket >
+ ((j + 1)*dwc_ep->maxpacket >
dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
- j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+ j*dwc_ep->maxpacket : dwc_ep->maxpacket;
data_per_desc +=
(data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
sts.b_iso_out.rxbytes = data_per_desc;
sts.b_iso_out.l = dwc_ep->proc_buf_num;
data_per_desc =
- ((j + 1) * dwc_ep->maxpacket >
+ ((j + 1)*dwc_ep->maxpacket >
dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
- j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+ j*dwc_ep->maxpacket : dwc_ep->maxpacket;
data_per_desc +=
(data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
sts.b_iso_out.rxbytes = data_per_desc;
dma_desc =
dwc_ep->iso_desc_addr +
- dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+ dwc_ep->desc_cnt*dwc_ep->proc_buf_num;
sts.b_iso_in.bs = BS_HOST_READY;
sts.b_iso_in.txsts = 0;
* @param dwc_ep The EP for wihich transfer complete was asserted
*
*/
-static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
- dwc_ep_t * dwc_ep)
-{
+static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t *core_if,
+ dwc_ep_t *dwc_ep) {
uint32_t dma_addr;
uint32_t drp_pkt;
uint32_t drp_pkt_cnt;
- deptsiz_data_t deptsiz = {.d32 = 0 };
- depctl_data_t depctl = {.d32 = 0 };
+ deptsiz_data_t deptsiz = {
+ .d32 = 0};
+ depctl_data_t depctl = {
+ .d32 = 0};
int i;
deptsiz.d32 =
if (deptsiz.b.pktcnt > 0) {
deptsiz.b.xfersize =
dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
- deptsiz.b.pktcnt) * dwc_ep->maxpacket;
+ deptsiz.b.pktcnt)*dwc_ep->maxpacket;
} else {
deptsiz.b.xfersize = 0;
deptsiz.b.pktcnt = 0;
* @param ep The EP to start the transfer on.
*
*/
-static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+static uint32_t set_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
{
int i, j;
dma_addr_t dma_ad;
* @param ep The EP for which transfer complete was asserted
*
*/
-static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
+static void complete_iso_ep(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
dwc_ep_t *dwc_ep = &ep->dwc_ep;
* This function handle BNA interrupt for Non Isochronous EPs
*
*/
-static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
+static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t *ep)
{
dwc_ep_t *dwc_ep = &ep->dwc_ep;
volatile uint32_t *addr;
- depctl_data_t depctl = {.d32 = 0 };
+ depctl_data_t depctl = {
+ .d32 = 0};
dwc_otg_pcd_t *pcd = ep->pcd;
dwc_otg_dev_dma_desc_t *dma_desc;
- dev_dma_desc_sts_t sts = {.d32 = 0 };
+ dev_dma_desc_sts_t sts = {
+ .d32 = 0};
dwc_otg_core_if_t *core_if = ep->pcd->core_if;
int i, start;
(dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
- && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
+ && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
uint32_t doepdma;
dwc_otg_dev_out_ep_regs_t *out_regs =
- core_if->dev_if->out_ep_regs[dwc_ep->num];
+ core_if->dev_if->out_ep_regs[dwc_ep->num];
doepdma = DWC_READ_REG32(&(out_regs->doepdma));
- start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
+ start =
+ (doepdma -
+ dwc_ep->dma_desc_addr) / sizeof(dwc_otg_dev_dma_desc_t);
dma_desc = &(dwc_ep->desc_addr[start]);
} else {
start = 0;
dma_desc = dwc_ep->desc_addr;
}
-
for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
sts.d32 = dma_desc->status.d32;
* The state of the control transfers are tracked in
* <code>ep0state</code>.
*/
-static void handle_ep0(dwc_otg_pcd_t * pcd)
+static void handle_ep0(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
/**
* Restart transfer
*/
-static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
+static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum)
{
dwc_otg_core_if_t *core_if;
dwc_otg_dev_if_t *dev_if;
- deptsiz_data_t dieptsiz = {.d32 = 0 };
+ deptsiz_data_t dieptsiz = {
+ .d32 = 0};
dwc_otg_pcd_ep_t *ep;
ep = get_in_ep(pcd, epnum);
*
* @param core_if Programming view of DWC_otg controller
*/
-void predict_nextep_seq( dwc_otg_core_if_t * core_if)
+void predict_nextep_seq(dwc_otg_core_if_t *core_if)
{
dwc_otg_device_global_regs_t *dev_global_regs =
core_if->dev_if->dev_global_regs;
uint32_t in_tkn_epnums[4];
uint8_t seqnum[MAX_EPS_CHANNELS];
uint8_t intkn_seq[TOKEN_Q_DEPTH];
- grstctl_t resetctl = {.d32 = 0 };
+ grstctl_t resetctl = {
+ .d32 = 0};
uint8_t temp;
int ndx = 0;
int start = 0;
if (seqnum[i + 1] != 0xff) {
core_if->nextep_seq[seqnum[i]] = seqnum[i + 1];
} else {
- core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
+ core_if->nextep_seq[seqnum[i]] =
+ core_if->first_in_nextep_seq;
break;
}
} else {
resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
resetctl.b.intknqflsh = 1;
DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-
}
/**
* handle the IN EP disable interrupt.
*/
-static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
+static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t *pcd,
const uint32_t epnum)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
- deptsiz_data_t dieptsiz = {.d32 = 0 };
- dctl_data_t dctl = {.d32 = 0 };
+ deptsiz_data_t dieptsiz = {
+ .d32 = 0};
+ dctl_data_t dctl = {
+ .d32 = 0};
dwc_otg_pcd_ep_t *ep;
dwc_ep_t *dwc_ep;
gintmsk_data_t gintmsk_data;
if (ep->stopped) {
if (core_if->en_multiple_tx_fifo)
/* Flush the Tx FIFO */
- dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
+ dwc_otg_flush_tx_fifo(core_if,
+ dwc_ep->tx_fifo_num);
/* Clear the Global IN NP NAK */
dctl.d32 = 0;
dctl.b.cgnpinnak = 1;
- DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl,
+ dctl.d32, dctl.d32);
/* Restart the transaction */
if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
restart_transfer(pcd, epnum);
return;
}
- if (core_if->start_predict > 2) { // NP IN EP
+ if (core_if->start_predict > 2) {
+ /* NP IN EP */
core_if->start_predict--;
return;
}
core_if->start_predict--;
- if (core_if->start_predict == 1) { // All NP IN Ep's disabled now
-
+ if (core_if->start_predict == 1) {
+ /* All NP IN Ep's disabled now */
predict_nextep_seq(core_if);
/* Update all active IN EP's NextEP field based of nextep_seq[] */
for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
depctl.d32 =
DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
- if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP
+ if (core_if->nextep_seq[i] != 0xff) {
+ /* Active NP IN EP */
depctl.b.nextep = core_if->nextep_seq[i];
- DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl,
+ depctl.d32);
}
}
/* Flush Shared NP TxFIFO */
dwc_otg_flush_tx_fifo(core_if, 0);
/* Rewind buffers */
- if (!core_if->dma_desc_enable) {
+ if (!core_if->dma_desc_enable) {
i = core_if->first_in_nextep_seq;
do {
ep = get_in_ep(pcd, i);
- dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
- xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
- if (xfer_size > ep->dwc_ep.maxxfer)
+ dieptsiz.d32 =
+ DWC_READ_REG32(&dev_if->
+ in_ep_regs[i]->dieptsiz);
+ xfer_size =
+ ep->dwc_ep.total_len -
+ ep->dwc_ep.xfer_count;
+ if (xfer_size > ep->dwc_ep.maxxfer)
xfer_size = ep->dwc_ep.maxxfer;
- depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+ depctl.d32 =
+ DWC_READ_REG32(&dev_if->
+ in_ep_regs[i]->diepctl);
if (dieptsiz.b.pktcnt != 0) {
if (xfer_size == 0) {
remain_to_transfer = 0;
} else {
- if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
- remain_to_transfer =
- dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
+ if ((xfer_size %
+ ep->dwc_ep.maxpacket) ==
+ 0) {
+ remain_to_transfer =
+ dieptsiz.b.pktcnt *
+ ep->
+ dwc_ep.maxpacket;
} else {
- remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
- + (xfer_size % ep->dwc_ep.maxpacket);
+ remain_to_transfer =
+ ((dieptsiz.
+ b.pktcnt -
+ 1) *
+ ep->
+ dwc_ep.maxpacket)
+ +
+ (xfer_size %
+ ep->
+ dwc_ep.maxpacket);
}
}
- diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
- dieptsiz.b.xfersize = remain_to_transfer;
- DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
- diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
- DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
+ diepdma =
+ DWC_READ_REG32(&dev_if->in_ep_regs
+ [i]->diepdma);
+ dieptsiz.b.xfersize =
+ remain_to_transfer;
+ DWC_WRITE_REG32(&dev_if->
+ in_ep_regs[i]->dieptsiz,
+ dieptsiz.d32);
+ diepdma =
+ ep->dwc_ep.dma_addr + (xfer_size -
+ remain_to_transfer);
+ DWC_WRITE_REG32(&dev_if->
+ in_ep_regs[i]->diepdma,
+ diepdma);
}
i = core_if->nextep_seq[i];
} while (i != core_if->first_in_nextep_seq);
- } else { // dma_desc_enable
- DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
+ } else { /* dma_desc_enable */
+ DWC_PRINTF("%s Learning Queue not supported in DDMA\n",
+ __func__);
}
-
+
/* Restart transfers in predicted sequences */
i = core_if->first_in_nextep_seq;
do {
- dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
- depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+ dieptsiz.d32 =
+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
+ depctl.d32 =
+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
if (dieptsiz.b.pktcnt != 0) {
- depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+ depctl.d32 =
+ DWC_READ_REG32(&dev_if->
+ in_ep_regs[i]->diepctl);
depctl.b.epena = 1;
depctl.b.cnak = 1;
- DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl,
+ depctl.d32);
}
i = core_if->nextep_seq[i];
} while (i != core_if->first_in_nextep_seq);
/* Clear the global non-periodic IN NAK handshake */
dctl.d32 = 0;
dctl.b.cgnpinnak = 1;
- DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-
+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32,
+ dctl.d32);
+
/* Unmask EP Mismatch interrupt */
gintmsk_data.d32 = 0;
gintmsk_data.b.epmismatch = 1;
- DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
-
+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
+ gintmsk_data.d32);
+
core_if->start_predict = 0;
- }
+ }
}
/**
* Handler for the IN EP timeout handshake interrupt.
*/
-static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
+static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd,
const uint32_t epnum)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
#ifdef DEBUG
- deptsiz_data_t dieptsiz = {.d32 = 0 };
+ deptsiz_data_t dieptsiz = {
+ .d32 = 0};
uint32_t num = 0;
#endif
- dctl_data_t dctl = {.d32 = 0 };
+ dctl_data_t dctl = {
+ .d32 = 0};
dwc_otg_pcd_ep_t *ep;
- gintmsk_data_t intr_mask = {.d32 = 0 };
+ gintmsk_data_t intr_mask = {
+ .d32 = 0};
ep = get_in_ep(pcd, epnum);
/**
* Handler for the IN EP NAK interrupt.
*/
-static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
+static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t *pcd,
const uint32_t epnum)
{
/** @todo implement ISR */
dwc_otg_core_if_t *core_if;
- diepmsk_data_t intr_mask = {.d32 = 0 };
+ diepmsk_data_t intr_mask = {
+ .d32 = 0};
DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
core_if = GET_CORE_IF(pcd);
/**
* Handler for the OUT EP Babble interrupt.
*/
-static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
+static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t *pcd,
const uint32_t epnum)
{
/** @todo implement ISR */
dwc_otg_core_if_t *core_if;
- doepmsk_data_t intr_mask = {.d32 = 0 };
+ doepmsk_data_t intr_mask = {
+ .d32 = 0};
DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
"OUT EP Babble");
/**
* Handler for the OUT EP NAK interrupt.
*/
-static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
+static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t *pcd,
const uint32_t epnum)
{
/** @todo implement ISR */
dwc_otg_core_if_t *core_if;
- doepmsk_data_t intr_mask = {.d32 = 0 };
+ doepmsk_data_t intr_mask = {
+ .d32 = 0};
- DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
+ DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n",
+ "OUT EP NAK");
core_if = GET_CORE_IF(pcd);
intr_mask.b.nak = 1;
/**
* Handler for the OUT EP NYET interrupt.
*/
-static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
+static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t *pcd,
const uint32_t epnum)
{
/** @todo implement ISR */
dwc_otg_core_if_t *core_if;
- doepmsk_data_t intr_mask = {.d32 = 0 };
+ doepmsk_data_t intr_mask = {
+ .d32 = 0};
DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
core_if = GET_CORE_IF(pcd);
* -# If "IN Token EP Mismatch" (disable, this is handled by EP
* Mismatch Interrupt)
*/
-static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
+static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t *pcd)
{
-#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
+#define CLEAR_IN_EP_INTR(__core_if, __epnum, __intr) \
do { \
- diepint_data_t diepint = {.d32=0}; \
+ diepint_data_t diepint = {.d32 = 0}; \
diepint.b.__intr = 1; \
DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
diepint.d32); \
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_dev_if_t *dev_if = core_if->dev_if;
- diepint_data_t diepint = {.d32 = 0 };
- depctl_data_t depctl = {.d32 = 0 };
+ diepint_data_t diepint = {
+ .d32 = 0};
+ depctl_data_t depctl = {
+ .d32 = 0};
uint32_t ep_intr;
uint32_t epnum = 0;
dwc_otg_pcd_ep_t *ep;
dwc_ep_t *dwc_ep;
- gintmsk_data_t intr_mask = {.d32 = 0 };
- dctl_data_t dctl = {.d32=0};
+ gintmsk_data_t intr_mask = {
+ .d32 = 0};
+ dctl_data_t dctl = {
+ .d32 = 0};
DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
if (core_if->en_multiple_tx_fifo == 0) {
intr_mask.b.nptxfempty = 1;
DWC_MODIFY_REG32
- (&core_if->core_global_regs->gintmsk,
+ (&core_if->
+ core_global_regs->gintmsk,
intr_mask.d32, 0);
} else {
/* Disable the Tx FIFO Empty Interrupt for this EP */
}
#endif /* DWC_UTE_PER_IO */
else {
- if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
- dwc_ep->bInterval > 1) {
- dwc_ep->frame_num += dwc_ep->bInterval;
- if (dwc_ep->frame_num > 0x3FFF)
- {
+ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC
+ && dwc_ep->bInterval > 1) {
+ dwc_ep->frame_num +=
+ dwc_ep->bInterval;
+ if (dwc_ep->frame_num > 0x3FFF) {
dwc_ep->frm_overrun = 1;
- dwc_ep->frame_num &= 0x3FFF;
- } else
+ dwc_ep->frame_num &=
+ 0x3FFF;
+ } else
dwc_ep->frm_overrun = 0;
}
complete_ep(ep);
- if(diepint.b.nak)
- CLEAR_IN_EP_INTR(core_if, epnum, nak);
+ if (diepint.b.nak)
+ CLEAR_IN_EP_INTR(core_if, epnum,
+ nak);
}
}
/* Endpoint disable */
DWC_ERROR("EP%d IN AHB Error\n", epnum);
/* Clear the bit in DIEPINTn for this interrupt */
DWC_ERROR("EP%d DEPDMA=0x%08x \n",
- epnum, core_if->dev_if->in_ep_regs[epnum]->diepdma);
+ epnum,
+ core_if->dev_if->
+ in_ep_regs[epnum]->diepdma);
CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
- dctl.d32= DWC_READ_REG32( &core_if->dev_if->dev_global_regs->dctl );
+ dctl.d32 =
+ DWC_READ_REG32(&core_if->
+ dev_if->dev_global_regs->
+ dctl);
dctl.b.sftdiscon = 1;
- DWC_WRITE_REG32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
+ DWC_WRITE_REG32(&core_if->
+ dev_if->dev_global_regs->dctl,
+ dctl.d32);
dwc_otg_disable_global_interrupts(core_if);
ep->pcd->vbus_status = 0;
- if(ep->pcd->conn_status){
- ep->pcd->conn_status = 0;
+ if (ep->pcd->conn_status) {
+ ep->pcd->conn_status = 0;
}
DWC_SPINUNLOCK(pcd->lock);
cil_pcd_stop(core_if);
epnum);
if (!ep->stopped && epnum != 0) {
- diepmsk_data_t diepmsk = {.d32 = 0 };
+ diepmsk_data_t diepmsk = {
+ .d32 = 0};
diepmsk.b.intktxfemp = 1;
if (core_if->multiproc_int_enable) {
DWC_MODIFY_REG32
- (&dev_if->dev_global_regs->diepeachintmsk
+ (&dev_if->
+ dev_global_regs->diepeachintmsk
[epnum], diepmsk.d32, 0);
} else {
DWC_MODIFY_REG32
- (&dev_if->dev_global_regs->diepmsk,
+ (&dev_if->
+ dev_global_regs->diepmsk,
diepmsk.d32, 0);
}
} else if (core_if->dma_desc_enable
&& epnum == 0
&& pcd->ep0state ==
EP0_OUT_STATUS_PHASE) {
- // EP0 IN set STALL
+ /* EP0 IN set STALL */
depctl.d32 =
DWC_READ_REG32(&dev_if->in_ep_regs
[epnum]->diepctl);
*/
if (dwc_ep->next_frame !=
0xffffffff)
- dwc_otg_pcd_handle_iso_bna(ep);
+ dwc_otg_pcd_handle_iso_bna
+ (ep);
} else
-#endif /* DWC_EN_ISOC */
+#endif /* DWC_EN_ISOC */
{
- dwc_otg_pcd_handle_noniso_bna(ep);
+ dwc_otg_pcd_handle_noniso_bna
+ (ep);
}
}
}
if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
depctl_data_t depctl;
if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
- ep->dwc_ep.frame_num = core_if->frame_num;
+ ep->dwc_ep.frame_num =
+ core_if->frame_num;
if (ep->dwc_ep.bInterval > 1) {
depctl.d32 = 0;
- depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
- if (ep->dwc_ep.frame_num & 0x1) {
- depctl.b.setd1pid = 1;
- depctl.b.setd0pid = 0;
+ depctl.d32 =
+ DWC_READ_REG32
+ (&dev_if->in_ep_regs
+ [epnum]->diepctl);
+ if (ep->
+ dwc_ep.frame_num &
+ 0x1) {
+ depctl.
+ b.setd1pid =
+ 1;
+ depctl.
+ b.setd0pid =
+ 0;
} else {
- depctl.b.setd0pid = 1;
- depctl.b.setd1pid = 0;
+ depctl.
+ b.setd0pid =
+ 1;
+ depctl.
+ b.setd1pid =
+ 0;
}
- DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
+ DWC_WRITE_REG32
+ (&dev_if->in_ep_regs
+ [epnum]->diepctl,
+ depctl.d32);
}
start_next_request(ep);
}
- ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
- if (dwc_ep->frame_num > 0x3FFF) {
+ ep->dwc_ep.frame_num +=
+ ep->dwc_ep.bInterval;
+ if (dwc_ep->frame_num > 0x3FFF) {
dwc_ep->frm_overrun = 1;
dwc_ep->frame_num &= 0x3FFF;
- } else
+ } else
dwc_ep->frm_overrun = 0;
}
* -# If "Setup Phase Done" process Setup Packet (See Standard USB
* Command Processing)
*/
-static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
+static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t *pcd)
{
-#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
+#define CLEAR_OUT_EP_INTR(__core_if, __epnum, __intr) \
do { \
- doepint_data_t doepint = {.d32=0}; \
+ doepint_data_t doepint = {.d32 = 0}; \
doepint.b.__intr = 1; \
DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
doepint.d32); \
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
uint32_t ep_intr;
- doepint_data_t doepint = {.d32 = 0 };
+ doepint_data_t doepint = {
+ .d32 = 0};
uint32_t epnum = 0;
dwc_otg_pcd_ep_t *ep;
dwc_ep_t *dwc_ep;
- dctl_data_t dctl = {.d32 = 0 };
- gintmsk_data_t gintmsk = {.d32 = 0 };
-
+ dctl_data_t dctl = {
+ .d32 = 0};
+ gintmsk_data_t gintmsk = {
+ .d32 = 0};
DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
if (epnum == 0) {
/* Clear the bit in DOEPINTn for this interrupt */
- CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
- if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
- DWC_DEBUGPL(DBG_PCDV, "in xfer xomplete DOEPINT=%x doepint=%x\n",
- DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
- doepint.d32);
- DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
- DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
-
- if (core_if->snpsid >= OTG_CORE_REV_3_00a
- && core_if->dma_enable == 0) {
+ CLEAR_OUT_EP_INTR(core_if, epnum,
+ xfercompl);
+ if (core_if->snpsid >=
+ OTG_CORE_REV_3_00a) {
+ DWC_DEBUGPL(DBG_PCDV,
+ "in xfer xomplete DOEPINT=%x doepint=%x\n",
+ DWC_READ_REG32
+ (&core_if->
+ dev_if->out_ep_regs
+ [0]->doepint),
+ doepint.d32);
+ DWC_DEBUGPL(DBG_PCDV,
+ "DOEPCTL=%x \n",
+ DWC_READ_REG32
+ (&core_if->
+ dev_if->out_ep_regs
+ [0]->doepctl));
+
+ if (core_if->snpsid >=
+ OTG_CORE_REV_3_00a
+ && core_if->dma_enable ==
+ 0) {
doepint_data_t doepint;
- doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[0]->doepint);
- if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
- CLEAR_OUT_EP_INTR(core_if, epnum, sr);
+ doepint.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ out_ep_regs[0]->
+ doepint);
+ if (pcd->ep0state ==
+ EP0_IDLE
+ && doepint.b.sr) {
+ CLEAR_OUT_EP_INTR
+ (core_if,
+ epnum, sr);
goto exit_xfercompl;
}
}
/* In case of DDMA look at SR bit to go to the Data Stage */
if (core_if->dma_desc_enable) {
- dev_dma_desc_sts_t status = {.d32 = 0};
- if (pcd->ep0state == EP0_IDLE) {
- status.d32 = core_if->dev_if->setup_desc_addr[core_if->
- dev_if->setup_desc_index]->status.d32;
- if(pcd->data_terminated) {
- pcd->data_terminated = 0;
- status.d32 = core_if->dev_if->out_desc_addr->status.d32;
- dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
+ dev_dma_desc_sts_t
+ status = {
+ .d32 = 0};
+ if (pcd->ep0state ==
+ EP0_IDLE) {
+ status.d32 =
+ core_if->dev_if->setup_desc_addr
+ [core_if->
+ dev_if->setup_desc_index]->status.
+ d32;
+ if (pcd->data_terminated) {
+ pcd->data_terminated
+ = 0;
+ status.d32
+ =
+ core_if->dev_if->out_desc_addr->status.d32;
+ dwc_memcpy
+ (&pcd->setup_pkt->req,
+ pcd->backup_buf,
+ 8);
}
if (status.b.sr) {
if (doepint.b.setup) {
- DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "DMA DESC EP0_IDLE SR=1 setup=1\n");
/* Already started data stage, clear setup */
- CLEAR_OUT_EP_INTR(core_if, epnum, setup);
- doepint.b.setup = 0;
- handle_ep0(pcd);
+ CLEAR_OUT_EP_INTR
+ (core_if,
+ epnum,
+ setup);
+ doepint.b.setup
+ =
+ 0;
+ handle_ep0
+ (pcd);
/* Prepare for more setup packets */
- if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
- pcd->ep0state == EP0_IN_DATA_PHASE) {
- ep0_out_start(core_if, pcd);
+ if (pcd->ep0state == EP0_IN_STATUS_PHASE || pcd->ep0state == EP0_IN_DATA_PHASE) {
+ ep0_out_start
+ (core_if,
+ pcd);
}
-
+
goto exit_xfercompl;
} else {
/* Prepare for more setup packets */
- DWC_DEBUGPL(DBG_PCDV,
- "EP0_IDLE SR=1 setup=0 new setup comes\n");
- ep0_out_start(core_if, pcd);
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "EP0_IDLE SR=1 setup=0 new setup comes\n");
+ ep0_out_start
+ (core_if,
+ pcd);
}
}
} else {
- dwc_otg_pcd_request_t *req;
- dev_dma_desc_sts_t status = {.d32 = 0};
- diepint_data_t diepint0;
- diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepint);
+ dwc_otg_pcd_request_t
+ *req;
+ dev_dma_desc_sts_t
+ status = {
+ .d32 = 0};
+ diepint_data_t
+ diepint0;
+ diepint0.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepint);
if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
- DWC_ERROR("EP0 is stalled/disconnected\n");
+ DWC_ERROR
+ ("EP0 is stalled/disconnected\n");
}
/* Clear IN xfercompl if set */
- if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
- || pcd->ep0state == EP0_IN_DATA_PHASE)) {
- DWC_WRITE_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepint, diepint0.d32);
+ if (diepint0.
+ b.xfercompl
+ &&
+ (pcd->ep0state
+ ==
+ EP0_IN_STATUS_PHASE
+ ||
+ pcd->ep0state
+ ==
+ EP0_IN_DATA_PHASE)) {
+ DWC_WRITE_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepint,
+ diepint0.d32);
}
- status.d32 = core_if->dev_if->setup_desc_addr[core_if->
- dev_if->setup_desc_index]->status.d32;
-
- if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
- && (pcd->ep0state == EP0_OUT_DATA_PHASE))
- status.d32 = core_if->dev_if->out_desc_addr->status.d32;
+ status.d32 =
+ core_if->dev_if->setup_desc_addr
+ [core_if->
+ dev_if->setup_desc_index]->status.
+ d32;
+
+ if (ep->
+ dwc_ep.xfer_count
+ !=
+ ep->
+ dwc_ep.total_len
+ &&
+ (pcd->ep0state
+ ==
+ EP0_OUT_DATA_PHASE))
+ status.d32
+ =
+ core_if->dev_if->out_desc_addr->status.d32;
if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
- status.d32 = core_if->dev_if->
- out_desc_addr->status.d32;
-
+ status.d32
+ =
+ core_if->dev_if->
+ out_desc_addr->status.d32;
+
if (status.b.sr) {
if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
- DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "Request queue empty!!\n");
} else {
- DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "complete req!!\n");
req = DWC_CIRCLEQ_FIRST(&ep->queue);
- if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
- pcd->ep0state == EP0_OUT_DATA_PHASE) {
- /* Read arrived setup packet from req->buf */
- dwc_memcpy(&pcd->setup_pkt->req,
- req->buf + ep->dwc_ep.xfer_count, 8);
+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && pcd->ep0state == EP0_OUT_DATA_PHASE) {
+ /* Read arrived setup packet from req->buf */
+ dwc_memcpy
+ (&pcd->setup_pkt->req,
+ req->buf
+ +
+ ep->dwc_ep.xfer_count,
+ 8);
}
- req->actual = ep->dwc_ep.xfer_count;
- dwc_otg_request_done(ep, req, -ECONNRESET);
+ req->actual
+ =
+ ep->dwc_ep.xfer_count;
+ dwc_otg_request_done
+ (ep,
+ req,
+ -ECONNRESET);
ep->dwc_ep.start_xfer_buff = 0;
ep->dwc_ep.xfer_buff = 0;
ep->dwc_ep.xfer_len = 0;
}
- pcd->ep0state = EP0_IDLE;
+ pcd->ep0state
+ =
+ EP0_IDLE;
if (doepint.b.setup) {
- DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "EP0_IDLE SR=1 setup=1\n");
/* Data stage started, clear setup */
- CLEAR_OUT_EP_INTR(core_if, epnum, setup);
- doepint.b.setup = 0;
- handle_ep0(pcd);
- /* Prepare for setup packets if ep0in was enabled*/
+ CLEAR_OUT_EP_INTR
+ (core_if,
+ epnum,
+ setup);
+ doepint.b.setup
+ =
+ 0;
+ handle_ep0
+ (pcd);
+ /* Prepare for setup packets if ep0in was enabled */
if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
- ep0_out_start(core_if, pcd);
+ ep0_out_start
+ (core_if,
+ pcd);
}
goto exit_xfercompl;
} else {
/* Prepare for more setup packets */
- DWC_DEBUGPL(DBG_PCDV,
- "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
- ep0_out_start(core_if, pcd);
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
+ ep0_out_start
+ (core_if,
+ pcd);
}
}
}
- }
- if (core_if->snpsid >= OTG_CORE_REV_3_00a && core_if->dma_enable
- && core_if->dma_desc_enable == 0) {
- doepint_data_t doepint_temp = {.d32 = 0};
- deptsiz0_data_t doeptsize0 = {.d32 = 0 };
- doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[ep->dwc_ep.num]->doepint);
- doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[ep->dwc_ep.num]->doeptsiz);
- if (((ep->dwc_ep.xfer_count == ep->dwc_ep.total_len || doeptsize0.b.xfersize == 64) &&
- pcd->ep0state == EP0_OUT_DATA_PHASE && doepint.b.stsphsercvd) ||
- (doeptsize0.b.xfersize == 24 && pcd->ep0state == EP0_IN_STATUS_PHASE)) {
- CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
- DWC_DEBUGPL(DBG_PCDV, "WA for xfercompl along with stsphs \n");
- doepint.b.xfercompl = 0;
- ep0_out_start(core_if, pcd);
- goto exit_xfercompl;
+ }
+ if (core_if->snpsid >=
+ OTG_CORE_REV_3_00a
+ && core_if->dma_enable
+ && core_if->dma_desc_enable
+ == 0) {
+ doepint_data_t
+ doepint_temp = {
+ .d32 = 0};
+ deptsiz0_data_t
+ doeptsize0 = {
+ .d32 = 0};
+ doepint_temp.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ out_ep_regs[ep->
+ dwc_ep.
+ num]->doepint);
+ doeptsize0.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ out_ep_regs[ep->
+ dwc_ep.
+ num]->doeptsiz);
+ if (((ep->
+ dwc_ep.xfer_count
+ ==
+ ep->
+ dwc_ep.total_len
+ || doeptsize0.
+ b.xfersize == 64)
+ && pcd->ep0state ==
+ EP0_OUT_DATA_PHASE
+ && doepint.
+ b.stsphsercvd)
+ || (doeptsize0.
+ b.xfersize == 24
+ && pcd->ep0state
+ ==
+ EP0_IN_STATUS_PHASE)){
+ CLEAR_OUT_EP_INTR
+ (core_if,
+ epnum,
+ xfercompl);
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "WA for xfercompl along with stsphs \n");
+ doepint.
+ b.xfercompl
+ = 0;
+ ep0_out_start
+ (core_if,
+ pcd);
+ goto exit_xfercompl;
}
- if (pcd->ep0state == EP0_IDLE) {
+ if (pcd->ep0state ==
+ EP0_IDLE) {
if (doepint_temp.b.sr) {
- CLEAR_OUT_EP_INTR(core_if, epnum, sr);
+ CLEAR_OUT_EP_INTR
+ (core_if,
+ epnum,
+ sr);
}
- /* Delay is needed for core to update setup
- * packet count from 3 to 2 after receiving
- * setup packet*/
- dwc_udelay(100);
- doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[0]->doepint);
- if (doeptsize0.b.supcnt == 3) {
- DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
- ep->dwc_ep.stp_rollover = 1;
- }
- if (doepint.b.setup) {
+ /* Delay is needed for core to update setup
+ * packet count from 3 to 2 after receiving
+ * setup packet*/
+ dwc_udelay(100);
+ doepint.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ out_ep_regs
+ [0]->doepint);
+ if (doeptsize0.b.supcnt == 3) {
+ DWC_DEBUGPL
+ (DBG_ANY,
+ "Rolling over!!!!!!!\n");
+ ep->dwc_ep.stp_rollover = 1;
+ }
+ if (doepint.
+ b.setup) {
retry:
- /* Already started data stage, clear setup */
- CLEAR_OUT_EP_INTR(core_if, epnum, setup);
- doepint.b.setup = 0;
- handle_ep0(pcd);
- ep->dwc_ep.stp_rollover = 0;
- /* Prepare for more setup packets */
- if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
- pcd->ep0state == EP0_IN_DATA_PHASE) {
- depctl_data_t depctl = {.d32 = 0};
- depctl.b.cnak = 1;
- ep0_out_start(core_if, pcd);
- /* Core not updating setup packet count
- * in case of PET testing - @TODO vahrama
- * to check with HW team further */
- if (!core_if->otg_ver) {
- DWC_MODIFY_REG32(&core_if->dev_if->
- out_ep_regs[0]->doepctl, 0, depctl.d32);
- }
+ /* Already started data stage, clear setup */
+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
+ doepint.b.setup
+ = 0;
+ handle_ep0
+ (pcd);
+ ep->dwc_ep.stp_rollover = 0;
+ /* Prepare for more setup packets */
+ if (pcd->ep0state == EP0_IN_STATUS_PHASE || pcd->ep0state == EP0_IN_DATA_PHASE) {
+ depctl_data_t
+ depctl
+ = {
+ .d32 = 0};
+ depctl.b.cnak
+ =
+ 1;
+ ep0_out_start
+ (core_if,
+ pcd);
+ /* Core not updating setup packet count
+ * in case of PET testing - @TODO vahrama
+ * to check with HW team further */
+ if (!core_if->otg_ver) {
+ DWC_MODIFY_REG32
+ (&core_if->dev_if->
+ out_ep_regs
+ [0]->doepctl,
+ 0,
+ depctl.d32);
}
- goto exit_xfercompl;
- } else {
- /* Prepare for more setup packets */
- DWC_DEBUGPL(DBG_ANY,
- "EP0_IDLE SR=1 setup=0 new setup comes\n");
- doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[0]->doepint);
- if(doepint.b.setup)
- goto retry;
- ep0_out_start(core_if, pcd);
}
+ goto exit_xfercompl;
+ } else {
+ /* Prepare for more setup packets */
+ DWC_DEBUGPL
+ (DBG_ANY,
+ "EP0_IDLE SR=1 setup=0 new setup comes\n");
+ doepint.d32
+ =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ out_ep_regs
+ [0]->doepint);
+ if (doepint.b.setup)
+ goto retry;
+ ep0_out_start
+ (core_if,
+ pcd);
+ }
} else {
- dwc_otg_pcd_request_t *req;
- diepint_data_t diepint0 = {.d32 = 0};
- doepint_data_t doepint_temp = {.d32 = 0};
- depctl_data_t diepctl0;
- diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepint);
- diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepctl);
-
- if (pcd->ep0state == EP0_IN_DATA_PHASE
- || pcd->ep0state == EP0_IN_STATUS_PHASE) {
+ dwc_otg_pcd_request_t
+ *req;
+ diepint_data_t
+ diepint0 = {
+ .d32 = 0};
+ doepint_data_t
+ doepint_temp
+ = {
+ .d32 = 0};
+ depctl_data_t
+ diepctl0;
+ diepint0.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepint);
+ diepctl0.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepctl);
+
+ if (pcd->ep0state == EP0_IN_DATA_PHASE || pcd->ep0state == EP0_IN_STATUS_PHASE) {
if (diepint0.b.xfercompl) {
- DWC_WRITE_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepint, diepint0.d32);
+ DWC_WRITE_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepint,
+ diepint0.d32);
}
if (diepctl0.b.epena) {
- diepint_data_t diepint = {.d32 = 0};
- diepctl0.b.snak = 1;
- DWC_WRITE_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepctl, diepctl0.d32);
+ diepint_data_t
+ diepint
+ = {
+ .d32 = 0};
+ diepctl0.b.snak
+ =
+ 1;
+ DWC_WRITE_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepctl,
+ diepctl0.d32);
do {
- dwc_udelay(10);
- diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepint);
- } while (!diepint.b.inepnakeff);
- diepint.b.inepnakeff = 1;
- DWC_WRITE_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepint, diepint.d32);
- diepctl0.d32 = 0;
- diepctl0.b.epdis = 1;
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
- diepctl0.d32);
+ dwc_udelay
+ (10);
+ diepint.d32
+ =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepint);
+ } while (!diepint.b.inepnakeff);
+ diepint.b.inepnakeff
+ =
+ 1;
+ DWC_WRITE_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepint,
+ diepint.d32);
+ diepctl0.d32
+ =
+ 0;
+ diepctl0.b.epdis
+ =
+ 1;
+ DWC_WRITE_REG32
+ (&core_if->dev_if->in_ep_regs
+ [0]->diepctl,
+ diepctl0.d32);
do {
- dwc_udelay(10);
- diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
- in_ep_regs[0]->diepint);
- } while (!diepint.b.epdisabled);
- diepint.b.epdisabled = 1;
- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
- diepint.d32);
+ dwc_udelay
+ (10);
+ diepint.d32
+ =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ in_ep_regs
+ [0]->diepint);
+ } while (!diepint.b.epdisabled);
+ diepint.b.epdisabled
+ =
+ 1;
+ DWC_WRITE_REG32
+ (&core_if->dev_if->in_ep_regs
+ [0]->diepint,
+ diepint.d32);
}
}
- doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[ep->dwc_ep.num]->doepint);
+ doepint_temp.d32
+ =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ out_ep_regs
+ [ep->dwc_ep.num]->doepint);
if (doepint_temp.b.sr) {
- CLEAR_OUT_EP_INTR(core_if, epnum, sr);
+ CLEAR_OUT_EP_INTR
+ (core_if,
+ epnum,
+ sr);
if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
- DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "Request queue empty!!\n");
} else {
- DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "complete req!!\n");
req = DWC_CIRCLEQ_FIRST(&ep->queue);
- if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
- pcd->ep0state == EP0_OUT_DATA_PHASE) {
- /* Read arrived setup packet from req->buf */
- dwc_memcpy(&pcd->setup_pkt->req,
- req->buf + ep->dwc_ep.xfer_count, 8);
+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && pcd->ep0state == EP0_OUT_DATA_PHASE) {
+ /* Read arrived setup packet from req->buf */
+ dwc_memcpy
+ (&pcd->setup_pkt->req,
+ req->buf
+ +
+ ep->dwc_ep.xfer_count,
+ 8);
}
- req->actual = ep->dwc_ep.xfer_count;
- dwc_otg_request_done(ep, req, -ECONNRESET);
+ req->actual
+ =
+ ep->dwc_ep.xfer_count;
+ dwc_otg_request_done
+ (ep,
+ req,
+ -ECONNRESET);
ep->dwc_ep.start_xfer_buff = 0;
ep->dwc_ep.xfer_buff = 0;
ep->dwc_ep.xfer_len = 0;
}
- pcd->ep0state = EP0_IDLE;
+ pcd->ep0state
+ =
+ EP0_IDLE;
if (doepint.b.setup) {
- DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "EP0_IDLE SR=1 setup=1\n");
/* Data stage started, clear setup */
- CLEAR_OUT_EP_INTR(core_if, epnum, setup);
- doepint.b.setup = 0;
- handle_ep0(pcd);
- /* Prepare for setup packets if ep0in was enabled*/
+ CLEAR_OUT_EP_INTR
+ (core_if,
+ epnum,
+ setup);
+ doepint.b.setup
+ =
+ 0;
+ handle_ep0
+ (pcd);
+ /* Prepare for setup packets if ep0in was enabled */
if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
- depctl_data_t depctl = {.d32 = 0};
- depctl.b.cnak = 1;
- ep0_out_start(core_if, pcd);
- /* Core not updating setup packet count
- * in case of PET testing - @TODO vahrama
- * to check with HW team further */
+ depctl_data_t
+ depctl
+ = {
+ .d32 = 0};
+ depctl.b.cnak
+ =
+ 1;
+ ep0_out_start
+ (core_if,
+ pcd);
+ /* Core not updating setup packet count
+ * in case of PET testing - @TODO vahrama
+ * to check with HW team further */
if (!core_if->otg_ver) {
- DWC_MODIFY_REG32(&core_if->dev_if->
- out_ep_regs[0]->doepctl, 0, depctl.d32);
+ DWC_MODIFY_REG32
+ (&core_if->dev_if->
+ out_ep_regs
+ [0]->doepctl,
+ 0,
+ depctl.d32);
}
}
goto exit_xfercompl;
} else {
/* Prepare for more setup packets */
- DWC_DEBUGPL(DBG_PCDV,
- "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
- ep0_out_start(core_if, pcd);
+ DWC_DEBUGPL
+ (DBG_PCDV,
+ "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
+ ep0_out_start
+ (core_if,
+ pcd);
}
}
}
- }
- if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
+ }
+ if (core_if->dma_enable == 0
+ || pcd->ep0state !=
+ EP0_IDLE)
handle_ep0(pcd);
exit_xfercompl:
- DWC_DEBUGPL(DBG_PCDV, "after DOEPINT=%x doepint=%x\n",
- dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
+ DWC_DEBUGPL(DBG_PCDV,
+ "after DOEPINT=%x doepint=%x\n",
+ dwc_otg_read_dev_out_ep_intr
+ (core_if, dwc_ep),
+ doepint.d32);
} else {
- if (core_if->dma_desc_enable == 0
- || pcd->ep0state != EP0_IDLE)
+ if (core_if->dma_desc_enable ==
+ 0
+ || pcd->ep0state !=
+ EP0_IDLE)
handle_ep0(pcd);
}
#ifdef DWC_EN_ISOC
complete_iso_ep(pcd, ep);
} else {
- doepint_data_t doepint = {.d32 = 0 };
+ doepint_data_t doepint = {
+ .d32 = 0};
doepint.b.xfercompl = 1;
doepint.b.pktdrpsts = 1;
DWC_WRITE_REG32
- (&core_if->dev_if->out_ep_regs
+ (&core_if->
+ dev_if->out_ep_regs
[epnum]->doepint,
doepint.d32);
if (handle_iso_out_pkt_dropped
#endif /* DWC_EN_ISOC */
#ifdef DWC_UTE_PER_IO
} else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
- CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
+ CLEAR_OUT_EP_INTR(core_if, epnum,
+ xfercompl);
if (!ep->stopped)
complete_xiso_ep(ep);
#endif /* DWC_UTE_PER_IO */
xfercompl);
if (core_if->core_params->dev_out_nak) {
- DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
- pcd->core_if->ep_xfer_info[epnum].state = 0;
+ DWC_TIMER_CANCEL(pcd->
+ core_if->ep_xfer_timer
+ [epnum]);
+ pcd->
+ core_if->ep_xfer_info
+ [epnum].state = 0;
#ifdef DEBUG
- print_memory_payload(pcd, dwc_ep);
+ print_memory_payload(pcd,
+ dwc_ep);
#endif
}
- complete_ep(ep);
+ complete_ep(ep);
}
}
deptsiz0_data_t deptsiz;
CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
deptsiz.d32 =
- DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[0]->doeptsiz);
- if ((core_if->dma_desc_enable) || (core_if->dma_enable &&
- core_if->snpsid >= OTG_CORE_REV_3_00a)) {
- do_setup_in_status_phase(pcd);
+ DWC_READ_REG32(&core_if->dev_if->
+ out_ep_regs[0]->doeptsiz);
+ if ((core_if->dma_desc_enable)
+ || (core_if->dma_enable
+ && core_if->snpsid >=
+ OTG_CORE_REV_3_00a)) {
+ do_setup_in_status_phase(pcd);
}
}
-
+
/* Endpoint disable */
if (doepint.b.epdisabled) {
print_memory_payload(pcd, dwc_ep);
#endif
/* In case of timeout condition */
- if (core_if->ep_xfer_info[epnum].state == 2) {
- dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
- dev_global_regs->dctl);
+ if (core_if->
+ ep_xfer_info[epnum].state == 2) {
+ dctl.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ dev_global_regs->dctl);
dctl.b.cgoutnak = 1;
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
- dctl.d32);
+ DWC_WRITE_REG32
+ (&core_if->dev_if->dev_global_regs->dctl,
+ dctl.d32);
/* Unmask goutnakeff interrupt which was masked
* during handle nak out interrupt */
gintmsk.b.goutnakeff = 1;
- DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
- 0, gintmsk.d32);
-
+ DWC_MODIFY_REG32
+ (&core_if->core_global_regs->gintmsk,
+ 0, gintmsk.d32);
+
complete_ep(ep);
}
}
- if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
- {
+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
dctl_data_t dctl;
- gintmsk_data_t intr_mask = {.d32 = 0};
+ gintmsk_data_t intr_mask = {
+ .d32 = 0};
dwc_otg_pcd_request_t *req = 0;
- dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
- dev_global_regs->dctl);
+ dctl.d32 =
+ DWC_READ_REG32(&core_if->dev_if->
+ dev_global_regs->dctl);
dctl.b.cgoutnak = 1;
- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
- dctl.d32);
+ DWC_WRITE_REG32(&core_if->
+ dev_if->dev_global_regs->
+ dctl, dctl.d32);
intr_mask.d32 = 0;
intr_mask.b.incomplisoout = 1;
/* Get any pending requests */
if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
- req = DWC_CIRCLEQ_FIRST(&ep->queue);
+ req =
+ DWC_CIRCLEQ_FIRST
+ (&ep->queue);
if (!req) {
- DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
+ DWC_PRINTF
+ ("complete_ep 0x%p, req = NULL!\n",
+ ep);
} else {
- dwc_otg_request_done(ep, req, 0);
+ dwc_otg_request_done(ep,
+ req,
+ 0);
start_next_request(ep);
}
} else {
- DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
+ DWC_PRINTF
+ ("complete_ep 0x%p, ep->queue empty!\n",
+ ep);
}
}
}
if (doepint.b.ahberr) {
DWC_ERROR("EP%d OUT AHB Error\n", epnum);
DWC_ERROR("EP%d DEPDMA=0x%08x \n",
- epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
+ epnum,
+ core_if->dev_if->
+ out_ep_regs[epnum]->doepdma);
CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
}
/* Setup Phase Done (contorl EPs) */
if (doepint.b.setup) {
#ifdef DEBUG_EP0
- DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
+ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n",
+ epnum);
#endif
CLEAR_OUT_EP_INTR(core_if, epnum, setup);
*/
if (dwc_ep->next_frame !=
0xffffffff)
- dwc_otg_pcd_handle_iso_bna(ep);
+ dwc_otg_pcd_handle_iso_bna
+ (ep);
} else
-#endif /* DWC_EN_ISOC */
+#endif /* DWC_EN_ISOC */
{
- dwc_otg_pcd_handle_noniso_bna(ep);
+ dwc_otg_pcd_handle_noniso_bna
+ (ep);
}
}
}
}
if (doepint.b.outtknepdis) {
DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
- disabled\n",epnum);
+ disabled\n",
+ epnum);
if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
- doepmsk_data_t doepmsk = {.d32 = 0};
- ep->dwc_ep.frame_num = core_if->frame_num;
+ doepmsk_data_t doepmsk = {
+ .d32 = 0};
+ ep->dwc_ep.frame_num =
+ core_if->frame_num;
if (ep->dwc_ep.bInterval > 1) {
depctl_data_t depctl;
- depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
- out_ep_regs[epnum]->doepctl);
+ depctl.d32 =
+ DWC_READ_REG32
+ (&core_if->dev_if->
+ out_ep_regs
+ [epnum]->doepctl);
if (ep->dwc_ep.frame_num & 0x1) {
depctl.b.setd1pid = 1;
depctl.b.setd0pid = 0;
depctl.b.setd0pid = 1;
depctl.b.setd1pid = 0;
}
- DWC_WRITE_REG32(&core_if->dev_if->
- out_ep_regs[epnum]->doepctl, depctl.d32);
+ DWC_WRITE_REG32
+ (&core_if->dev_if->
+ out_ep_regs
+ [epnum]->doepctl,
+ depctl.d32);
}
start_next_request(ep);
doepmsk.b.outtknepdis = 1;
- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
- doepmsk.d32, 0);
+ DWC_MODIFY_REG32(&core_if->
+ dev_if->dev_global_regs->doepmsk,
+ doepmsk.d32, 0);
}
CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
}
#undef CLEAR_OUT_EP_INTR
}
-static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
+
+static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr,
+ uint8_t frm_overrun)
{
int retval = 0;
- if(!frm_overrun && curr_fr >= trgt_fr)
+ if (!frm_overrun && curr_fr >= trgt_fr)
retval = 1;
else if (frm_overrun
&& (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
* -# Disable EP; when "Endpoint Disabled" interrupt is received
* Flush FIFO
*/
-int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t *pcd)
{
gintsts_data_t gintsts;
#ifdef DWC_EN_ISOC
dwc_otg_dev_if_t *dev_if;
- deptsiz_data_t deptsiz = {.d32 = 0 };
- depctl_data_t depctl = {.d32 = 0 };
- dsts_data_t dsts = {.d32 = 0 };
+ deptsiz_data_t deptsiz = {
+ .d32 = 0};
+ depctl_data_t depctl = {
+ .d32 = 0};
+ dsts_data_t dsts = {
+ .d32 = 0};
dwc_ep_t *dwc_ep;
int i;
}
#else
- depctl_data_t depctl = {.d32 = 0 };
+ depctl_data_t depctl = {
+ .d32 = 0};
dwc_ep_t *dwc_ep;
dwc_otg_dev_if_t *dev_if;
int i;
dev_if = GET_CORE_IF(pcd)->dev_if;
- DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
-
+ DWC_DEBUGPL(DBG_PCD, "Incomplete ISO IN \n");
+
for (i = 1; i <= dev_if->num_in_eps; ++i) {
- dwc_ep = &pcd->in_ep[i-1].dwc_ep;
- depctl.d32 =
- DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+ dwc_ep = &pcd->in_ep[i - 1].dwc_ep;
+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
- if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
- dwc_ep->frm_overrun))
- {
+ if (drop_transfer
+ (dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
+ dwc_ep->frm_overrun)) {
depctl.d32 =
- DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+ DWC_READ_REG32(&dev_if->
+ in_ep_regs[i]->diepctl);
depctl.b.snak = 1;
depctl.b.epdis = 1;
- DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
+ DWC_MODIFY_REG32(&dev_if->
+ in_ep_regs[i]->diepctl,
+ depctl.d32, depctl.d32);
}
}
}
/*intr_mask.b.incomplisoin = 1;
DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
intr_mask.d32, 0); */
-#endif //DWC_EN_ISOC
+#endif /* DWC_EN_ISOC */
/* Clear interrupt */
gintsts.d32 = 0;
* -# Disable EP. When "Endpoint Disabled" interrupt is received
* re-enable EP.
*/
-int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t *pcd)
{
gintsts_data_t gintsts;
#ifdef DWC_EN_ISOC
dwc_otg_dev_if_t *dev_if;
- deptsiz_data_t deptsiz = {.d32 = 0 };
- depctl_data_t depctl = {.d32 = 0 };
- dsts_data_t dsts = {.d32 = 0 };
+ deptsiz_data_t deptsiz = {
+ .d32 = 0};
+ depctl_data_t depctl = {
+ .d32 = 0};
+ dsts_data_t dsts = {
+ .d32 = 0};
dwc_ep_t *dwc_ep;
int i;
}
#else
/** @todo implement ISR */
- gintmsk_data_t intr_mask = {.d32 = 0 };
+ gintmsk_data_t intr_mask = {
+ .d32 = 0};
dwc_otg_core_if_t *core_if;
- deptsiz_data_t deptsiz = {.d32 = 0 };
- depctl_data_t depctl = {.d32 = 0 };
- dctl_data_t dctl = {.d32 = 0 };
+ deptsiz_data_t deptsiz = {
+ .d32 = 0};
+ depctl_data_t depctl = {
+ .d32 = 0};
+ dctl_data_t dctl = {
+ .d32 = 0};
dwc_ep_t *dwc_ep = NULL;
int i;
core_if = GET_CORE_IF(pcd);
for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
dwc_ep = &pcd->out_ep[i].dwc_ep;
depctl.d32 =
- DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
- if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
- core_if->dev_if->isoc_ep = dwc_ep;
+ DWC_READ_REG32(&core_if->dev_if->
+ out_ep_regs[dwc_ep->num]->doepctl);
+ if (depctl.b.epena
+ && depctl.b.dpid == (core_if->frame_num & 0x1)) {
+ core_if->dev_if->isoc_ep = dwc_ep;
deptsiz.d32 =
- DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
- break;
+ DWC_READ_REG32(&core_if->
+ dev_if->out_ep_regs[dwc_ep->num]->
+ doeptsiz);
+ break;
}
}
dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
if (!intr_mask.b.goutnakeff) {
/* Unmask it */
intr_mask.b.goutnakeff = 1;
- DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
- }
+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk,
+ intr_mask.d32);
+ }
if (!gintsts.b.goutnakeff) {
dctl.b.sgoutnak = 1;
}
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
- depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
+ depctl.d32 =
+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
if (depctl.b.epena) {
depctl.b.epdis = 1;
depctl.b.snak = 1;
}
- DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl,
+ depctl.d32);
intr_mask.d32 = 0;
intr_mask.b.incomplisoout = 1;
-
+
#endif /* DWC_EN_ISOC */
/* Clear interrupt */
* This function handles the Global IN NAK Effective interrupt.
*
*/
-int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t *pcd)
{
dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
- depctl_data_t diepctl = {.d32 = 0 };
- gintmsk_data_t intr_mask = {.d32 = 0 };
+ depctl_data_t diepctl = {
+ .d32 = 0};
+ gintmsk_data_t intr_mask = {
+ .d32 = 0};
gintsts_data_t gintsts;
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
int i;
core_if->start_predict++;
diepctl.b.epdis = 1;
diepctl.b.snak = 1;
- DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
- }
+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl,
+ diepctl.d32);
+ }
}
-
/* Disable the Global IN NAK Effective Interrupt */
intr_mask.b.ginnakeff = 1;
* OUT NAK Effective.
*
*/
-int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t *pcd)
{
dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
- gintmsk_data_t intr_mask = {.d32 = 0 };
+ gintmsk_data_t intr_mask = {
+ .d32 = 0};
gintsts_data_t gintsts;
depctl_data_t doepctl;
int i;
/* If DEV OUT NAK enabled */
if (pcd->core_if->core_params->dev_out_nak) {
/* Run over all out endpoints to determine the ep number on
- * which the timeout has happened
+ * which the timeout has happened
*/
for (i = 0; i <= dev_if->num_out_eps; i++) {
if (pcd->core_if->ep_xfer_info[i].state == 2)
* All interrupt registers are processed from LSB to MSB.
*
*/
-int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
+int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
#ifdef VERBOSE
#endif
gintsts_data_t gintr_status;
int32_t retval = 0;
-
- if (dwc_otg_check_haps_status(core_if) == -1 ) {
- DWC_WARN("HAPS is disconnected");
+
+ if (dwc_otg_check_haps_status(core_if) == -1) {
+ DWC_WARN("HAPS is disconnected");
return retval;
}
projects / firefly-linux-kernel-4.4.55.git / blobdiff