video: exynos_dp: Fix incorrect setting for INT_CTL

[firefly-linux-kernel-4.4.55.git] / drivers / video / exynos / exynos_dp_reg.h

diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h
index 125b27cd57aebd3f44acf997cf08f711928b61dd..2e9bd0e0b9f2e1fc722b6c9ca0db4708f8cd4898 100644 (file)
--- a/drivers/video/exynos/exynos_dp_reg.h
+++ b/drivers/video/exynos/exynos_dp_reg.h
@@ -187,7 +187,7 @@
 #define PD_RING_OSC                            (0x1 << 6)
 #define AUX_TERMINAL_CTRL_50_OHM               (0x2 << 4)
 #define TX_CUR1_2X                             (0x1 << 2)
-#define TX_CUR_8_MA                            (0x2 << 0)
+#define TX_CUR_16_MA                           (0x3 << 0)
 
 /* EXYNOS_DP_TX_AMP_TUNING_CTL */
 #define CH3_AMP_400_MV                         (0x0 << 24)
@@ -242,7 +242,8 @@
 
 /* EXYNOS_DP_INT_CTL */
 #define SOFT_INT_CTRL                          (0x1 << 2)
-#define INT_POL                                        (0x1 << 0)
+#define INT_POL1                               (0x1 << 1)
+#define INT_POL0                               (0x1 << 0)
 
 /* EXYNOS_DP_SYS_CTL_1 */
 #define DET_STA                                        (0x1 << 2)
@@ -285,6 +286,7 @@
 #define SW_TRAINING_PATTERN_SET_NORMAL         (0x0 << 0)
 
 /* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+#define PRE_EMPHASIS_SET_MASK                  (0x3 << 3)
 #define PRE_EMPHASIS_SET_SHIFT                 (3)
 
 /* EXYNOS_DP_DEBUG_CTL */