/* fill in known card constants if pll_block is not available */
static void aty128_timings(struct aty128fb_par *par)
{
-#ifdef CONFIG_PPC_OF
+#ifdef CONFIG_PPC
/* instead of a table lookup, assume OF has properly
* setup the PLL registers and use their values
* to set the XCLK values and reference divider values */
if (!par->constants.ref_clk)
par->constants.ref_clk = 2950;
-#ifdef CONFIG_PPC_OF
+#ifdef CONFIG_PPC
x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;