/* Color Space Convertion Mode */
enum {
CSC_RGB_0_255_TO_RGB_16_235_8BIT, /* RGB 0-255 input to RGB
- 16-235 output that is 8bit
- clolor depth */
+ * 16-235 output that is 8bit
+ * clolor depth
+ */
CSC_RGB_0_255_TO_RGB_16_235_10BIT, /* RGB 0-255 input to RGB
- 16-235 output that is 8bit
- clolor depth */
+ * 16-235 output that is 8bit
+ * clolor depth
+ */
CSC_RGB_0_255_TO_ITU601_16_235_8BIT, /* RGB 0-255 input to YCbCr
- 16-235 output according
- BT601 that is 8bit clolor
- depth */
+ * 16-235 output according
+ * BT601 that is 8bit clolor
+ * depth
+ */
CSC_RGB_0_255_TO_ITU601_16_235_10BIT, /* RGB 0-255 input to YCbCr
- 16-235 output according
- BT601 that is 10bit clolor
- depth */
+ * 16-235 output according
+ * BT601 that is 10bit clolor
+ * depth
+ */
CSC_RGB_0_255_TO_ITU709_16_235_8BIT, /* RGB 0-255 input to YCbCr
- 16-235 output accroding
- BT709 that is 8bit clolor
- depth */
+ * 16-235 output accroding
+ * BT709 that is 8bit clolor
+ * depth
+ */
CSC_RGB_0_255_TO_ITU709_16_235_10BIT, /* RGB 0-255 input to YCbCr
- 16-235 output accroding
- BT709 that is 10bit clolor
- depth */
- CSC_ITU601_16_235_TO_RGB_16_235_8BIT, /* YCbCr 16-235 input to RGB
- 16-235 output according
- BT601 that is 8bit clolor
- depth */
- CSC_ITU709_16_235_TO_RGB_16_235_8BIT, /* YCbCr 16-235 input to RGB
- 16-235 output according
- BT709 that is 8bit clolor
- depth */
+ * 16-235 output accroding
+ * BT709 that is 10bit clolor
+ * depth
+ */
CSC_ITU601_16_235_TO_RGB_0_255_8BIT, /* YCbCr 16-235 input to RGB
- 0-255 output according
- BT601 that is 8bit clolor
- depth */
- CSC_ITU709_16_235_TO_RGB_0_255_8BIT /* YCbCr 16-235 input to RGB
- 0-255 output according
- BT709 that is 8bit clolor
- depth */
+ * 0-255 output according
+ * BT601 that is 8bit clolor
+ * depth
+ */
+ CSC_ITU709_16_235_TO_RGB_0_255_8BIT, /* YCbCr 16-235 input to RGB
+ * 0-255 output according
+ * BT709 that is 8bit clolor
+ * depth
+ */
+ CSC_ITU601_16_235_TO_RGB_16_235_8BIT, /* YCbCr 16-235 input to RGB
+ * 16-235 output according
+ * BT601 that is 8bit clolor
+ * depth
+ */
+ CSC_ITU709_16_235_TO_RGB_16_235_8BIT /* YCbCr 16-235 input to RGB
+ * 16-235 output according
+ * BT709 that is 8bit clolor
+ * depth
+ */
};
#define HDMI_SCL_RATE (100*1000)
#define m_HDCP (1 << 0)
#define CONFIG1_ID 0x0005
+#define m_HDCP22 (1 << 6)
#define m_HDMI20 (1 << 5)
#define m_CONFAPB (1 << 1)
#define m_AVI_INFOFRAME (1 << 1)
#define m_GCP (1 << 0)
+#define v_AVI_INFOFRAME(n) (((n)&0x01) << 1)
+
#define IH_FC_STAT2 0x0102
#define m_LOWPRIO_OVERFLOW (1 << 1)
#define m_HIGHPRIO_OVERFLOW (1 << 0)
#define FC_PRCONF 0x10e0
#define m_FC_PR_FACTOR (0x0f << 4)
#define v_FC_PR_FACTOR(n) (((n)&0x0f) << 4)
+#define m_FC_PR_FACTOR_OUT (0x0f)
+#define v_FC_PR_FACTOR_OUT(n) ((n) & 0x0f)
#define FC_SCRAMBLER_CTRL 0x10e1
#define m_FC_SCRAMBLE_UCP (1 << 4)
#define m_HDCP2_AUTH_LOST (1 << 2)
#define m_HDCP2_AUTH_OK (1 << 3)
#define m_HDCP2_AUTH_FAIL (1 << 4)
+ #define m_HDCP2_DECRYPTED_CHG (1 << 5)
/* CEC Engine Registers */
#define CEC_ENGINE_BASE 0x7d00
#define v_SLOPEBOOST(n) (((n)&0x03) << 4)
#define m_TX_SYMON (0x01 << 3)
#define v_TX_SYMON(n) (((n)&0x01) << 3)
-#define m_TX_TRAON (0x01 << 2)
-#define v_TX_TRAON(n) (((n)&0x01) << 2)
-#define m_TX_TRBON (0x01 << 1)
-#define v_TX_TRBON(n) (((n)&0x01) << 1)
+#define m_PREEMPHASIS (0x03 << 1)
+#define v_PREEMPHASIS(n) (((n)&0x03) << 1)
#define m_CLK_SYMON (0x01 << 0)
#define v_CLK_SYMON(n) (((n)&0x01) << 0)
u16 gmp_cntrl;
};
+/* PHY Defined for RK322X */
+#define EXT_PHY_CONTROL 0
+ #define EXT_PHY_ANALOG_RESET_MASK 0x80
+ #define EXT_PHY_DIGITAL_RESET_MASK 0x40
+ #define EXT_PHY_PCLK_INVERT_MASK 0x08
+ #define EXT_PHY_PREPCLK_INVERT_MASK 0x04
+ #define EXT_PHY_TMDSCLK_INVERT_MASK 0x02
+ #define EXT_PHY_SRC_SELECT_MASK 0x01
+
+#define EXT_PHY_TERM_CAL 0x03
+ #define EXT_PHY_TERM_CAL_EN_MASK 0x80
+ #define EXT_PHY_TERM_CAL_DIV_H_MASK 0x7f
+
+#define EXT_PHY_TERM_CAL_DIV_L 0x04
+
+#define EXT_PHY_PLL_PRE_DIVIDER 0xe2
+ #define EXT_PHY_PLL_FB_BIT8_MASK 0x80
+ #define EXT_PHY_PLL_PCLK_DIV5_EN_MASK 0x20
+ #define EXT_PHY_PLL_PRE_DIVIDER_MASK 0x1f
+
+#define EXT_PHY_PLL_FB_DIVIDER 0xe3
+
+#define EXT_PHY_PCLK_DIVIDER1 0xe4
+ #define EXT_PHY_PCLK_DIVIDERB_MASK 0x60
+ #define EXT_PHY_PCLK_DIVIDERA_MASK 0x1f
+
+#define EXT_PHY_PCLK_DIVIDER2 0xe5
+ #define EXT_PHY_PCLK_DIVIDERC_MASK 0x60
+ #define EXT_PHY_PCLK_DIVIDERD_MASK 0x1f
+
+#define EXT_PHY_TMDSCLK_DIVIDER 0xe6
+ #define EXT_PHY_TMDSCLK_DIVIDERC_MASK 0x30
+ #define EXT_PHY_TMDSCLK_DIVIDERA_MASK 0x0c
+ #define EXT_PHY_TMDSCLK_DIVIDERB_MASK 0x03
+
+#define EXT_PHY_PLL_BW 0xe7
+
+#define EXT_PHY_PPLL_PRE_DIVIDER 0xe9
+ #define EXT_PHY_PPLL_ENABLE_MASK 0xc0
+ #define EXT_PHY_PPLL_PRE_DIVIDER_MASK 0x1f
+
+#define EXT_PHY_PPLL_FB_DIVIDER 0xea
+
+#define EXT_PHY_PPLL_POST_DIVIDER 0xeb
+ #define EXT_PHY_PPLL_FB_DIVIDER_BIT8_MASK 0x80
+ #define EXT_PHY_PPLL_POST_DIVIDER_MASK 0x30
+ #define EXT_PHY_PPLL_LOCK_STATUS_MASK 0x01
+
+#define EXT_PHY_PPLL_BW 0xec
+
+#define EXT_PHY_SIGNAL_CTRL 0xee
+ #define EXT_PHY_TRANSITION_CLK_EN_MASK 0x80
+ #define EXT_PHY_TRANSITION_D0_EN_MASK 0x40
+ #define EXT_PHY_TRANSITION_D1_EN_MASK 0x20
+ #define EXT_PHY_TRANSITION_D2_EN_MASK 0x10
+ #define EXT_PHY_LEVEL_CLK_EN_MASK 0x08
+ #define EXT_PHY_LEVEL_D0_EN_MASK 0x04
+ #define EXT_PHY_LEVEL_D1_EN_MASK 0x02
+ #define EXT_PHY_LEVEL_D2_EN_MASK 0x01
+
+#define EXT_PHY_SLOPEBOOST 0xef
+ #define EXT_PHY_SLOPEBOOST_CLK_MASK 0x03
+ #define EXT_PHY_SLOPEBOOST_D0_MASK 0x0c
+ #define EXT_PHY_SLOPEBOOST_D1_MASK 0x30
+ #define EXT_PHY_SLOPEBOOST_D2_MASK 0xc0
+
+#define EXT_PHY_PREEMPHASIS 0xf0
+ #define EXT_PHY_PREEMPHASIS_D0_MASK 0x03
+ #define EXT_PHY_PREEMPHASIS_D1_MASK 0x0c
+ #define EXT_PHY_PREEMPHASIS_D2_MASK 0x30
+
+#define EXT_PHY_LEVEL1 0xf1
+ #define EXT_PHY_LEVEL_CLK_MASK 0xf0
+ #define EXT_PHY_LEVEL_D2_MASK 0x0f
+
+#define EXT_PHY_LEVEL2 0xf2
+ #define EXT_PHY_LEVEL_D1_MASK 0xf0
+ #define EXT_PHY_LEVEL_D0_MASK 0x0f
+
+#define EXT_PHY_TERM_RESIS_AUTO 0xf4
+ #define EXT_PHY_AUTO_R50_OHMS 0
+ #define EXT_PHY_AUTO_R75_OHMS (1 << 2)
+ #define EXT_PHY_AUTO_R100_OHMS (2 << 2)
+ #define EXT_PHY_AUTO_ROPEN_CIRCUIT (3 << 2)
+
+#define EXT_PHY_TERM_RESIS_MANUAL_CLK 0xfb
+#define EXT_PHY_TERM_RESIS_MANUAL_D2 0xfc
+#define EXT_PHY_TERM_RESIS_MANUAL_D1 0xfd
+#define EXT_PHY_TERM_RESIS_MANUAL_D0 0xfe
+
+#define RK322X_DDC_MASK_EN ((3 << 13) | (3 << (13 + 16)))
+#define RK322X_IO_3V_DOMAIN ((7 << 4) | (7 << (4 + 16)))
+#define RK322X_PLL_POWER_DOWN (BIT(12) | BIT(12 + 16))
+#define RK322X_PLL_POWER_UP BIT(12 + 16)
+#define RK322X_PLL_PDATA_DEN BIT(11 + 16)
+#define RK322X_PLL_PDATA_EN (BIT(11) | BIT(11 + 16))
+
+struct ext_pll_config_tab {
+ u32 pix_clock;
+ u32 tmdsclock;
+ u8 color_depth;
+ u8 pll_nd;
+ u16 pll_nf;
+ u8 tmsd_divider_a;
+ u8 tmsd_divider_b;
+ u8 tmsd_divider_c;
+ u8 pclk_divider_a;
+ u8 pclk_divider_b;
+ u8 pclk_divider_c;
+ u8 pclk_divider_d;
+ u8 vco_div_5;
+ u8 ppll_nd;
+ u8 ppll_nf;
+ u8 ppll_no;
+};
/*
* HDMI TX PHY Define End
*/
void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev);
void rockchip_hdmiv2_cec_init(struct hdmi *hdmi);
void rockchip_hdmiv2_cec_isr(struct hdmi_dev *hdmi_dev, char cec_int);
-void rockchip_hdmiv2_dump_phy_regs(struct hdmi_dev *hdmi_dev);
void rockchip_hdmiv2_hdcp_init(struct hdmi *hdmi);
+void rockchip_hdmiv2_hdcp2_enable(int enable);
+void rockchip_hdmiv2_hdcp_isr(struct hdmi_dev *hdmi_dev, int hdcp_int);
+int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
+ int reg_addr, int val);
+int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
+ int reg_addr);
#endif
projects / firefly-linux-kernel-4.4.55.git / blobdiff