#define m_DITHER_UP_EN (1<<9)
#define m_INTERLACE_DSP_EN (1<<12)
#define m_INTERLACE_DSP_POL (1<<13)
+ #define m_WIN0_INTERLACE_EN (1<<14)
#define m_WIN1_INTERLACE_EN (1<<15)
#define m_WIN0_YRGB_DEFLICK_EN (1<<16)
#define m_WIN0_CBR_DEFLICK_EN (1<<17)
#define v_DITHER_UP_EN(x) (((x)&1)<<9)
#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
#define v_INTERLACE_DSP_POL(x) (((x)&1)<<13)
+ #define v_WIN0_INTERLACE_EN(x) (((x)&1)<<14)
#define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15)
#define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16)
#define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17)
spinlock_t reg_lock; /* one time only one process allowed to
config the register*/
+ int __iomem *hwc_lut_addr_base;
int __iomem *dsp_lut_addr_base;
u32 pixclock;
u32 standby; /*1:standby,0:work*/
+ u32 iommu_status;
};
static inline