#define CalScale(x, y) ((((u32)(x - 1)) * 0x1000) / (y - 1))
+#define INT_STA_MSK (m_HS_INT_STA | m_FS_INT_STA | \
+ m_LF_INT_STA | m_BUS_ERR_INT_STA)
+#define INT_CLR_SHIFT 8
struct rk_lcdc_drvdata {
u8 soc_type;
u32 reg_phy_base; /* physical basic address of lcdc register */
u32 len; /* physical map length of lcdc register */
spinlock_t reg_lock; /* one time only one process allowed to config the register */
-
+
+ int __iomem *hwc_lut_addr_base;
int __iomem *dsp_lut_addr_base;
int prop; /* used for primary or extended display device */
bool pre_init;
bool pwr18; /* if lcdc use 1.8v power supply */
bool clk_on; /* if aclk or hclk is closed ,acess to register is not allowed */
+ bool sclk_on; /* if sclk is open or closed */
u8 atv_layer_cnt; /* active layer counter,when atv_layer_cnt = 0,lcdc is disable*/
unsigned int irq;
u32 s_pixclock;
u32 standby; /* 1:standby,0:work */
+ struct backlight_device *backlight;
+ u32 iommu_status;
};
static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v)
}
static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset)
+{
+ u32 v;
+ v = readl_relaxed(lcdc_dev->regs + offset);
+ return v;
+}
+
+static inline u32 lcdc_readl_backup(struct lcdc_device *lcdc_dev, u32 offset)
{
u32 v;
u32 *_pv = (u32*)lcdc_dev->regsbak;