video: rockchip: tve: fix compile error and warning

[firefly-linux-kernel-4.4.55.git] / drivers / video / rockchip / lcdc / rk312x_lcdc.h

diff --git a/drivers/video/rockchip/lcdc/rk312x_lcdc.h b/drivers/video/rockchip/lcdc/rk312x_lcdc.h
index f880202dde6e0a0d160e13a50b60fd8d834d3bea..ec1d3cece51b4213e80cd166ecd7e3985c36f717 100755 (executable)
--- a/drivers/video/rockchip/lcdc/rk312x_lcdc.h
+++ b/drivers/video/rockchip/lcdc/rk312x_lcdc.h
@@ -174,7 +174,7 @@ enum _VOP_SOC_TYPE {
         #define v_FS_MASK_EN(x)                 BITS_MASK(x, 1, 3)
         #define v_HDMI_HSYNC_POL(x)             BITS_MASK(x, 1, 4)
         #define v_HDMI_VSYNC_POL(x)             BITS_MASK(x, 1, 5)
-        #define v_HDMI_DEN_POL(x)               BITS_MASK(x. 1, 6)
+        #define v_HDMI_DEN_POL(x)               BITS_MASK(x, 1, 6)
 
 #define INT_STATUS             (0x10)
         #define m_HS_INT_STA           BITS(1, 0)
@@ -415,7 +415,7 @@ enum _VOP_SOC_TYPE {
        #define v_BCSH_EN(x)            BITS_MASK(x, 1, 0)
         #define v_BCSH_R2Y_CSC_MODE(x)  BITS_MASK(x, 1, 1)       /* rk312x */
        #define v_BCSH_OUT_MODE(x)      BITS_MASK(x, 3, 2)
-       #define v_BCSH_CSC_MODE(x)      BITS_MASK(x, 3, 4)
+       #define v_BCSH_Y2R_CSC_MODE(x)  BITS_MASK(x, 3, 4)
         #define v_BCSH_Y2R_EN(x)        BITS_MASK(x, 1, 6)       /* rk312x */
         #define v_BCSH_R2Y_EN(x)        BITS_MASK(x, 1, 7)       /* rk312x */
 
@@ -649,6 +649,9 @@ enum _vop_overlay_mode {
 
 
 #define CalScale(x, y)              ((((u32)(x - 1)) * 0x1000) / (y - 1))
+#define INT_STA_MSK    (m_HS_INT_STA | m_FS_INT_STA |          \
+                        m_LF_INT_STA | m_BUS_ERR_INT_STA)
+#define INT_CLR_SHIFT  8
 
 struct rk_lcdc_drvdata {
      u8 soc_type;
@@ -667,13 +670,15 @@ struct lcdc_device {
        u32 reg_phy_base;               /* physical basic address of lcdc register */
        u32 len;                        /* physical map length of lcdc register */
        spinlock_t  reg_lock;           /* one time only one process allowed to config the register */
-       
+
+       int __iomem *hwc_lut_addr_base;
        int __iomem *dsp_lut_addr_base;
 
        int prop;                       /* used for primary or extended display device */
        bool pre_init;
        bool pwr18;                     /* if lcdc use 1.8v power supply */
        bool clk_on;                    /* if aclk or hclk is closed ,acess to register is not allowed */
+       bool sclk_on;                   /* if sclk is open or closed */
        u8 atv_layer_cnt;               /* active layer counter,when atv_layer_cnt = 0,lcdc is disable*/
 
        unsigned int            irq;
@@ -683,11 +688,13 @@ struct lcdc_device {
        struct clk              *dclk;  /* lcdc dclk */
        struct clk              *aclk;  /* lcdc share memory frequency */
         struct clk              *sclk;  /* scaler clk */
+       struct clk              *pll_sclk;
        u32 pixclock;
         u32 s_pixclock;
 
        u32 standby;                    /* 1:standby,0:work */
-       u16 overlay_mode;
+       struct backlight_device *backlight;
+       u32 iommu_status;
 };
 
 static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v)
@@ -699,6 +706,13 @@ static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v)
 }
 
 static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset)
+{
+       u32 v;
+       v = readl_relaxed(lcdc_dev->regs + offset);
+       return v;
+}
+
+static inline u32 lcdc_readl_backup(struct lcdc_device *lcdc_dev, u32 offset)
 {
        u32 v;
        u32 *_pv = (u32*)lcdc_dev->regsbak;