#ifndef _RGA_DRIVER_H_\r
#define _RGA_DRIVER_H_\r
\r
-#include "rga_type.h"\r
-#include <linux/types.h>\r
-#include <linux/miscdevice.h>\r
-#include <linux/platform_device.h>\r
-\r
+#include <linux/mutex.h>\r
\r
#define RGA_BLIT_SYNC 0x5017\r
#define RGA_BLIT_ASYNC 0x5018\r
#define RGA_FLUSH 0x5019\r
+#define RGA_GET_RESULT 0x501a\r
+#define RGA_GET_VERSION 0x501b\r
\r
\r
#define RGA_REG_CTRL_LEN 0x8 /* 8 */\r
#define RGA_REG_CMD_LEN 0x1c /* 28 */\r
#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */\r
\r
+#define RGA_OUT_OF_RESOURCES -10\r
+#define RGA_MALLOC_ERROR -11\r
+\r
+\r
+#define rgaIS_ERROR(status) (status < 0)\r
+#define rgaNO_ERROR(status) (status >= 0)\r
+#define rgaIS_SUCCESS(status) (status == 0)\r
+\r
+\r
\r
/* RGA process mode enum */\r
enum\r
\r
typedef struct rga_img_info_t\r
{\r
- uint32 yrgb_addr; /* yrgb mem addr */\r
- uint32 uv_addr; /* cb/cr mem addr */\r
- uint32 v_addr; /* cr mem addr */\r
- uint32 format; //definition by RK_FORMAT\r
+ unsigned int yrgb_addr; /* yrgb mem addr */\r
+ unsigned int uv_addr; /* cb/cr mem addr */\r
+ unsigned int v_addr; /* cr mem addr */\r
+ unsigned int format; //definition by RK_FORMAT\r
\r
- UWORD16 act_w;\r
- UWORD16 act_h;\r
- UWORD16 x_offset;\r
- UWORD16 y_offset;\r
+ unsigned short act_w;\r
+ unsigned short act_h;\r
+ unsigned short x_offset;\r
+ unsigned short y_offset;\r
\r
- UWORD16 vir_w;\r
- UWORD16 vir_h;\r
+ unsigned short vir_w;\r
+ unsigned short vir_h;\r
\r
- UWORD16 endian_mode; //for BPP\r
- UWORD16 alpha_swap;\r
+ unsigned short endian_mode; //for BPP\r
+ unsigned short alpha_swap;\r
}\r
rga_img_info_t;\r
\r
\r
typedef struct mdp_img_act\r
{\r
- UWORD16 w; // width\r
- UWORD16 h; // height\r
- WORD16 x_off; // x offset for the vir\r
- WORD16 y_off; // y offset for the vir\r
+ unsigned short w; // width\r
+ unsigned short h; // height\r
+ short x_off; // x offset for the vir\r
+ short y_off; // y offset for the vir\r
}\r
mdp_img_act;\r
\r
\r
typedef struct RANGE\r
{\r
- UWORD16 min;\r
- UWORD16 max;\r
+ unsigned short min;\r
+ unsigned short max;\r
}\r
RANGE;\r
\r
typedef struct POINT\r
{\r
- UWORD16 x;\r
- UWORD16 y;\r
+ unsigned short x;\r
+ unsigned short y;\r
}\r
POINT;\r
\r
typedef struct RECT\r
{\r
- WORD16 xmin;\r
- WORD16 xmax; // width - 1\r
- WORD16 ymin; \r
- WORD16 ymax; // height - 1 \r
+ unsigned short xmin;\r
+ unsigned short xmax; // width - 1\r
+ unsigned short ymin; \r
+ unsigned short ymax; // height - 1 \r
} RECT;\r
\r
typedef struct RGB\r
typedef struct MMU\r
{\r
unsigned char mmu_en;\r
- uint32 base_addr;\r
- uint32 mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/\r
+ uint32_t base_addr;\r
+ uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/\r
} MMU;\r
\r
\r
\r
typedef struct FADING\r
{\r
- UBYTE b;\r
- UBYTE g;\r
- UBYTE r;\r
- UBYTE res;\r
+ uint8_t b;\r
+ uint8_t g;\r
+ uint8_t r;\r
+ uint8_t res;\r
}\r
FADING;\r
\r
\r
typedef struct line_draw_t\r
{\r
- POINT start_point; /* LineDraw_start_point */\r
- POINT end_point; /* LineDraw_end_point */\r
- uint32 color; /* LineDraw_color */\r
- uint32 flag; /* (enum) LineDrawing mode sel */\r
- uint32 line_width; /* range 1~16 */\r
+ POINT start_point; /* LineDraw_start_point */\r
+ POINT end_point; /* LineDraw_end_point */\r
+ uint32_t color; /* LineDraw_color */\r
+ uint32_t flag; /* (enum) LineDrawing mode sel */\r
+ uint32_t line_width; /* range 1~16 */\r
}\r
line_draw_t;\r
\r
\r
\r
struct rga_req {\r
- UBYTE render_mode; /* (enum) process mode sel */\r
+ uint8_t render_mode; /* (enum) process mode sel */\r
\r
- rga_img_info_t src; /* src image info */\r
- rga_img_info_t dst; /* dst image info */\r
- rga_img_info_t pat; /* patten image info */\r
+ rga_img_info_t src; /* src image info */\r
+ rga_img_info_t dst; /* dst image info */\r
+ rga_img_info_t pat; /* patten image info */\r
\r
- uint32 rop_mask_addr; /* rop4 mask addr */\r
- uint32 LUT_addr; /* LUT addr */\r
+ uint32_t rop_mask_addr; /* rop4 mask addr */\r
+ uint32_t LUT_addr; /* LUT addr */\r
\r
- RECT clip; /* dst clip window default value is dst_vir */\r
- /* value from [0, w-1] / [0, h-1]*/\r
+ RECT clip; /* dst clip window default value is dst_vir */\r
+ /* value from [0, w-1] / [0, h-1]*/\r
\r
- int32_t sina; /* dst angle default value 0 16.16 scan from table */\r
- int32_t cosa; /* dst angle default value 0 16.16 scan from table */ \r
-\r
- uint16_t alpha_rop_flag; /* alpha rop process flag */\r
- /* ([0] = 1 alpha_rop_enable) */\r
- /* ([1] = 1 rop enable) */ \r
- /* ([2] = 1 fading_enable) */\r
- /* ([3] = 1 PD_enable) */\r
- /* ([4] = 1 alpha cal_mode_sel) */\r
- /* ([5] = 1 dither_enable) */\r
- /* ([6] = 1 gradient fill mode sel) */\r
- /* ([7] = 1 AA_enable) */\r
-\r
- uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ \r
+ int32_t sina; /* dst angle default value 0 16.16 scan from table */\r
+ int32_t cosa; /* dst angle default value 0 16.16 scan from table */ \r
+\r
+ uint16_t alpha_rop_flag; /* alpha rop process flag */\r
+ /* ([0] = 1 alpha_rop_enable) */\r
+ /* ([1] = 1 rop enable) */ \r
+ /* ([2] = 1 fading_enable) */\r
+ /* ([3] = 1 PD_enable) */\r
+ /* ([4] = 1 alpha cal_mode_sel) */\r
+ /* ([5] = 1 dither_enable) */\r
+ /* ([6] = 1 gradient fill mode sel) */\r
+ /* ([7] = 1 AA_enable) */\r
+\r
+ uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ \r
\r
- uint32 color_key_max; /* color key max */\r
- uint32 color_key_min; /* color key min */ \r
+ uint32_t color_key_max; /* color key max */\r
+ uint32_t color_key_min; /* color key min */ \r
\r
- uint32 fg_color; /* foreground color */\r
- uint32 bg_color; /* background color */\r
+ uint32_t fg_color; /* foreground color */\r
+ uint32_t bg_color; /* background color */\r
\r
- COLOR_FILL gr_color; /* color fill use gradient */\r
+ COLOR_FILL gr_color; /* color fill use gradient */\r
\r
line_draw_t line_draw_info;\r
\r
FADING fading;\r
\r
- uint8_t PD_mode; /* porter duff alpha mode sel */\r
+ uint8_t PD_mode; /* porter duff alpha mode sel */\r
\r
- uint8_t alpha_global_value; /* global alpha value */\r
+ uint8_t alpha_global_value; /* global alpha value */\r
\r
- uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/\r
+ uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/\r
\r
- uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/\r
+ uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/\r
\r
- uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/\r
+ uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/\r
\r
- uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ \r
+ uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ \r
\r
- uint8_t endian_mode; /* 0/big endian 1/little endian*/\r
+ uint8_t endian_mode; /* 0/big endian 1/little endian*/\r
\r
- uint8_t rotate_mode; /* (enum) rotate mode */\r
- /* 0x0, no rotate */\r
- /* 0x1, rotate */\r
- /* 0x2, x_mirror */\r
- /* 0x3, y_mirror */\r
+ uint8_t rotate_mode; /* (enum) rotate mode */\r
+ /* 0x0, no rotate */\r
+ /* 0x1, rotate */\r
+ /* 0x2, x_mirror */\r
+ /* 0x3, y_mirror */\r
\r
- uint8_t color_fill_mode; /* 0 solid color / 1 patten color */\r
+ uint8_t color_fill_mode; /* 0 solid color / 1 patten color */\r
\r
- MMU mmu_info; /* mmu information */\r
+ MMU mmu_info; /* mmu information */\r
\r
- uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */\r
- /* ([2~3] rop mode) */\r
- /* ([4] zero mode en) */\r
- /* ([5] dst alpha mode) */\r
+ uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */\r
+ /* ([2~3] rop mode) */\r
+ /* ([4] zero mode en) */\r
+ /* ([5] dst alpha mode) */\r
\r
- uint8_t src_trans_mode;\r
-\r
- uint8_t CMD_fin_int_enable; \r
-\r
- /* completion is reported through a callback */\r
- void (*complete)(int retval);\r
+ uint8_t src_trans_mode; \r
};\r
\r
\r
/* a linked list of register data in processing */\r
struct list_head running;\r
/* all coommand this thread done */\r
- uint32_t done;\r
+ atomic_t done;\r
wait_queue_head_t wait;\r
pid_t pid;\r
atomic_t task_running;\r
+ atomic_t num_done;\r
} rga_session;\r
\r
-struct rga_reg {\r
+struct rga_reg { \r
rga_session *session;\r
struct list_head session_link; /* link to rga service session */\r
struct list_head status_link; /* link to register set list */\r
uint32_t sys_reg[RGA_REG_CTRL_LEN];\r
uint32_t cmd_reg[RGA_REG_CMD_LEN];\r
+ \r
uint32_t *MMU_base;\r
- atomic_t int_enable;\r
+ //atomic_t int_enable; \r
+\r
+ //struct rga_req req;\r
};\r
\r
\r
\r
typedef struct rga_service_info {\r
- spinlock_t lock;\r
+ struct mutex lock;\r
struct timer_list timer; /* timer for power off */\r
struct list_head waiting; /* link to link_reg in struct vpu_reg */\r
struct list_head running; /* link to link_reg in struct vpu_reg */\r
struct list_head done; /* link to link_reg in struct vpu_reg */\r
struct list_head session; /* link to list_session in struct vpu_session */\r
atomic_t total_running;\r
- bool enabled;\r
+ \r
struct rga_reg *reg;\r
- uint32_t cmd_buff[28*16];/* cmd_buff for rga */\r
+ \r
+ uint32_t cmd_buff[28*8];/* cmd_buff for rga */\r
uint32_t *pre_scale_buf;\r
atomic_t int_disable; /* 0 int enable 1 int disable */\r
-} rga_service_info;\r
-\r
-\r
-\r
-\r
-struct rga_drvdata {\r
- struct miscdevice miscdev;\r
- struct device dev;\r
- void *rga_base;\r
- int irq0;\r
-\r
- struct clk *pd_display;\r
- struct clk *aclk_lcdc;\r
- struct clk *hclk_lcdc;\r
- struct clk *aclk_ddr_lcdc;\r
- struct clk *hclk_cpu_display;\r
- struct clk *aclk_disp_matrix;\r
- struct clk *hclk_disp_matrix;\r
- struct clk *axi_clk;\r
- struct clk *ahb_clk;\r
- \r
- struct mutex mutex; // mutex\r
- \r
- struct delayed_work power_off_work;\r
- bool enable; //clk enable or disable\r
- void (*rga_irq_callback)(int rga_retval); //callback function used by aync call\r
-};\r
+ atomic_t cmd_num;\r
+ atomic_t src_format_swt;\r
+ int last_prc_src_format;\r
+ atomic_t rga_working;\r
+ bool enable;\r
\r
+ //struct rga_req req[10];\r
\r
+ struct mutex mutex; // mutex\r
+} rga_service_info;\r
\r
\r
\r
+#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)\r
+#define RGA_BASE 0x1010c000\r
+#elif defined(CONFIG_ARCH_RK30)\r
#define RGA_BASE 0x10114000\r
+#endif\r
\r
//General Registers\r
#define RGA_SYS_CTRL 0x000\r
\r
#define RGA_BLIT_COMPLETE_EVENT 1\r
\r
-\r
+long rga_ioctl_kernel(struct rga_req *req);\r
\r
\r
#endif /*_RK29_IPP_DRIVER_H_*/\r
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