Merge tag 'lsk-v3.10-android-15.01'

[firefly-linux-kernel-4.4.55.git] / drivers / video / rockchip / rga / rga_reg_info.c

diff --git a/drivers/video/rockchip/rga/rga_reg_info.c b/drivers/video/rockchip/rga/rga_reg_info.c
index cfb9465194f32d03f73bbfb69d75053be98b932f..b7bbf1d21f74b971c4e2a3c79170d5f43199adf3 100755 (executable)
--- a/drivers/video/rockchip/rga/rga_reg_info.c
+++ b/drivers/video/rockchip/rga/rga_reg_info.c
@@ -673,10 +673,13 @@ Date:
 s32 RGA_set_dst(u8 *base, const struct rga_req *msg)\r
 {\r
     u32 *bRGA_DST_MST;\r
+    u32 *bRGA_DST_UV_MST;\r
     u32 *bRGA_DST_VIR_INFO;\r
     u32 *bRGA_DST_CTR_INFO;\r
     u32 *bRGA_PRESCL_CB_MST;\r
     u32 *bRGA_PRESCL_CR_MST;\r
+    u32 *bRGA_YUV_OUT_CFG;\r
+\r
     u32 reg = 0;\r
 \r
     u8 pw;\r
@@ -685,10 +688,12 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
     u16 stride, rop_mask_stride;\r
 \r
     bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);\r
+    bRGA_DST_UV_MST = (u32 *)(base + RGA_DST_UV_MST_OFFSET);\r
     bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);\r
     bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);\r
     bRGA_PRESCL_CB_MST = (u32 *)(base + RGA_PRESCL_CB_MST_OFFSET);\r
     bRGA_PRESCL_CR_MST = (u32 *)(base + RGA_PRESCL_CR_MST_OFFSET);\r
+    bRGA_YUV_OUT_CFG = (u32 *)(base + RGA_YUV_OUT_CFG_OFFSET);\r
 \r
     pw = RGA_pixel_width_init(msg->dst.format);\r
 \r
@@ -696,39 +701,46 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
 \r
     *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw);\r
 \r
-    if (msg->render_mode == pre_scaling_mode)\r
+    *bRGA_DST_UV_MST = 0;\r
+    *bRGA_YUV_OUT_CFG = 0;\r
+    switch(msg->dst.format)\r
     {\r
-        switch(msg->dst.format)\r
-        {\r
-            case RK_FORMAT_YCbCr_422_SP :\r
-                *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
-                break;\r
-            case RK_FORMAT_YCbCr_422_P  :\r
-                *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
-                *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off) * stride) + ((x_off>>1) * pw);\r
-                break;\r
-            case RK_FORMAT_YCbCr_420_SP :\r
-                *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
-                break;\r
-            case RK_FORMAT_YCbCr_420_P :\r
-                *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
-                *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
-                break;\r
-            case RK_FORMAT_YCrCb_422_SP :\r
-                *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
-                break;\r
-            case RK_FORMAT_YCrCb_422_P  :\r
-                *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
-                *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off) * stride) + ((x_off>>1) * pw);\r
-                break;\r
-            case RK_FORMAT_YCrCb_420_SP :\r
-                *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
-                break;\r
-            case RK_FORMAT_YCrCb_420_P :\r
-                *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
-                *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
-                break;\r
-        }\r
+        case RK_FORMAT_YCbCr_422_SP :\r
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
+            *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off));\r
+            *bRGA_YUV_OUT_CFG |= (0 << 3) | 1 | (((msg->yuv2rgb_mode >> 4) & 3) << 4);\r
+            break;\r
+        case RK_FORMAT_YCbCr_422_P  :\r
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off) * stride) + ((x_off>>1) * pw);\r
+            break;\r
+        case RK_FORMAT_YCbCr_420_SP :\r
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
+            *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off));\r
+            *bRGA_YUV_OUT_CFG |= (0 << 3)|(1 << 1) | 1 | (((msg->yuv2rgb_mode >> 4) & 3) << 4);\r
+            break;\r
+        case RK_FORMAT_YCbCr_420_P :\r
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+            break;\r
+        case RK_FORMAT_YCrCb_422_SP :\r
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
+            *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off));\r
+            *bRGA_YUV_OUT_CFG |= (1 << 3)|(0 << 1) | 1 | (((msg->yuv2rgb_mode >> 4) & 3) << 4);\r
+            break;\r
+        case RK_FORMAT_YCrCb_422_P  :\r
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off) * stride) + ((x_off>>1) * pw);\r
+            break;\r
+        case RK_FORMAT_YCrCb_420_SP :\r
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
+            *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off));\r
+            *bRGA_YUV_OUT_CFG |= (1 << 3)|(1 << 1) | 1 | (((msg->yuv2rgb_mode >> 4) & 3) << 4);\r
+            break;\r
+        case RK_FORMAT_YCrCb_420_P :\r
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+            break;\r
     }\r
 \r
     rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21\r
@@ -750,6 +762,10 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
     *bRGA_DST_VIR_INFO = reg;\r
     *bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);\r
 \r
+    if (msg->render_mode == pre_scaling_mode) {\r
+        *bRGA_YUV_OUT_CFG &= 0xfffffffe;\r
+    }\r
+\r
     return 0;\r
 }\r
 \r