Merge branch 'linus' into x86/header-guards

[firefly-linux-kernel-4.4.55.git] / include / asm-arm / assembler.h

diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index add451ab89473948804619434181e9b216cdef6c..911393b2c6f000cc39bf84d73a7385883c105e5f 100644 (file)
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -55,12 +55,20 @@
 #define PLD(code...)
 #endif
 
-#define MODE_USR       USR_MODE
-#define MODE_FIQ       FIQ_MODE
-#define MODE_IRQ       IRQ_MODE
-#define MODE_SVC       SVC_MODE
-
-#define DEFAULT_FIQ    MODE_FIQ
+/*
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory.  Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
+ */
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
+#else
+#define CALGN(code...)
+#endif
 
 /*
  * Enable and disable interrupts
@@ -100,18 +108,6 @@
        msr     cpsr_c, \oldcpsr
        .endm
 
-/*
- * These two are used to save LR/restore PC over a user-based access.
- * The old 26-bit architecture requires that we do.  On 32-bit
- * architecture, we can safely ignore this requirement.
- */
-       .macro  save_lr
-       .endm
-
-       .macro  restore_pc
-       mov     pc, lr
-       .endm
-
 #define USER(x...)                             \
 9999:  x;                                      \
        .section __ex_table,"a";                \