ARM64: DTS: Fix Firefly board audio driver

[firefly-linux-kernel-4.4.55.git] / include / dt-bindings / clock / rk3399-cru.h

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 0715e66db20a29b2df23d8fdf727a48d6db78ecd..4b782158fab4d9412e5d66ca176cc265b54cffa3 100644 (file)
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -16,6 +16,8 @@
 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
 
+#define RK3399_TWO_PLL_FOR_VOP
+
 /* core clocks */
 #define PLL_APLLL                      1
 #define PLL_APLLB                      2
@@ -24,9 +26,8 @@
 #define PLL_GPLL                       5
 #define PLL_NPLL                       6
 #define PLL_VPLL                       7
-#define PLL_PPLL                       8
-#define ARMCLKL                                9
-#define ARMCLKB                                10
+#define ARMCLKL                                8
+#define ARMCLKB                                9
 
 /* sclk gates (special clocks) */
 #define SCLK_I2C1                      65
@@ -73,7 +74,7 @@
 #define SCLK_MACREF_OUT                        106
 #define SCLK_VOP0_PWM                  107
 #define SCLK_VOP1_PWM                  108
-#define SCLK_RGA                       109
+#define SCLK_RGA_CORE                  109
 #define SCLK_ISP0                      110
 #define SCLK_ISP1                      111
 #define SCLK_HDMI_CEC                  112
@@ -130,10 +131,26 @@
 #define SCLK_DPHY_TX0_CFG              163
 #define SCLK_DPHY_TX1RX1_CFG           164
 #define SCLK_DPHY_RX0_CFG              165
+#define SCLK_RMII_SRC                  166
+#define SCLK_PCIEPHY_REF100M           167
+#define SCLK_USBPHY0_480M_SRC          168
+#define SCLK_USBPHY1_480M_SRC          169
+#define SCLK_DDRCLK                    170
+#define SCLK_TESTOUT2                  171
+#define SCLK_UART0_SRC                 172
+#define SCLK_UART_SRC                  173
+#define SCLK_I2S0_DIV                  174
+#define SCLK_I2S1_DIV                  175
+#define SCLK_I2S2_DIV                  176
+#define SCLK_SPDIF_DIV                 177
+#define SCLK_I2S_8CH                   178
+
 
 #define DCLK_VOP0                      180
 #define DCLK_VOP1                      181
-#define DCLK_M0_PERILP                 182
+#define DCLK_VOP0_DIV                  182
+#define DCLK_VOP1_DIV                  183
+#define DCLK_M0_PERILP                 184
 
 #define FCLK_CM0S                      190
 
@@ -209,6 +226,8 @@
 #define ACLK_PERF_CORE_L               260
 #define ACLK_PERF_CORE_B               261
 #define ACLK_GIC_PRE                   262
+#define ACLK_VOP0_PRE                  263
+#define ACLK_VOP1_PRE                  264
 
 /* pclk gates */
 #define PCLK_PERIHP                    320
@@ -337,16 +356,19 @@
 #define CLK_NR_CLKS                    (HCLK_SDIOAUDIO_NOC + 1)
 
 /* pmu-clocks indices */
-#define SCLK_32K_SUSPEND_PMU           0
-#define SCLK_SPI3_PMU                  1
-#define SCLK_TIMER12_PMU               2
-#define SCLK_TIMER13_PMU               3
-#define SCLK_UART4_PMU                 4
-#define SCLK_PVTM_PMU                  5
-#define SCLK_WIFI_PMU                  6
-#define SCLK_I2C0_PMU                  7
-#define SCLK_I2C4_PMU                  8
-#define SCLK_I2C8_PMU                  9
+
+#define PLL_PPLL                       1
+
+#define SCLK_32K_SUSPEND_PMU           2
+#define SCLK_SPI3_PMU                  3
+#define SCLK_TIMER12_PMU               4
+#define SCLK_TIMER13_PMU               5
+#define SCLK_UART4_PMU                 6
+#define SCLK_PVTM_PMU                  7
+#define SCLK_WIFI_PMU                  8
+#define SCLK_I2C0_PMU                  9
+#define SCLK_I2C4_PMU                  10
+#define SCLK_I2C8_PMU                  11
 
 #define PCLK_SRC_PMU                   19
 #define PCLK_PMU                       20
@@ -590,13 +612,13 @@
 #define SRST_P_SPI0                    214
 #define SRST_P_SPI1                    215
 #define SRST_P_SPI2                    216
-#define SRST_P_SPI3                    217
-#define SRST_P_SPI4                    218
+#define SRST_P_SPI4                    217
+#define SRST_P_SPI5                    218
 #define SRST_SPI0                      219
 #define SRST_SPI1                      220
 #define SRST_SPI2                      221
-#define SRST_SPI3                      222
-#define SRST_SPI4                      223
+#define SRST_SPI4                      222
+#define SRST_SPI5                      223
 
 /* cru_softrst_con14 */
 #define SRST_I2S0_8CH                  224
@@ -665,6 +687,7 @@
 #define SRST_P_EDP_CTRL                        285
 
 /* cru_softrst_con18 */
+#define SRST_A_GPU                     288
 #define SRST_A_GPU_NOC                 289
 #define SRST_A_GPU_GRF                 290
 #define SRST_PVTM_GPU                  291
@@ -717,8 +740,8 @@
 #define SRST_H_CM0S_NOC                        3
 #define SRST_DBG_CM0S                  4
 #define SRST_PO_CM0S                   5
-#define SRST_P_SPI6                    6
-#define SRST_SPI6                      7
+#define SRST_P_SPI3                    6
+#define SRST_SPI3                      7
 #define SRST_P_TIMER_0_1               8
 #define SRST_P_TIMER_0                 9
 #define SRST_P_TIMER_1                 10