#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+#define RK3399_TWO_PLL_FOR_VOP
+
/* core clocks */
#define PLL_APLLL 1
#define PLL_APLLB 2
#define PLL_GPLL 5
#define PLL_NPLL 6
#define PLL_VPLL 7
-#define PLL_PPLL 8
-#define ARMCLKL 9
-#define ARMCLKB 10
+#define ARMCLKL 8
+#define ARMCLKB 9
/* sclk gates (special clocks) */
#define SCLK_I2C1 65
#define SCLK_MACREF_OUT 106
#define SCLK_VOP0_PWM 107
#define SCLK_VOP1_PWM 108
-#define SCLK_RGA 109
+#define SCLK_RGA_CORE 109
#define SCLK_ISP0 110
#define SCLK_ISP1 111
#define SCLK_HDMI_CEC 112
#define SCLK_HDMI_SFR 113
-#define SCLK_DP_CORE_SRC 114
+#define SCLK_DP_CORE 114
#define SCLK_PVTM_CORE_L 115
#define SCLK_PVTM_CORE_B 116
#define SCLK_PVTM_GPU 117
#define SCLK_CIF_OUT 137
#define SCLK_PCIEPHY_REF 138
#define SCLK_PCIE_CORE 139
-#define SCLK_MO_PERILP 140
+#define SCLK_M0_PERILP 140
#define SCLK_M0_PERILP_DEC 141
#define SCLK_CM0S 142
#define SCLK_DBG_NOC 143
#define SCLK_INTMEM3 151
#define SCLK_INTMEM4 152
#define SCLK_INTMEM5 153
-
-#define DCLK_VOP0 170
-#define DCLK_VOP1 171
+#define SCLK_SDMMC_DRV 154
+#define SCLK_SDMMC_SAMPLE 155
+#define SCLK_SDIO_DRV 156
+#define SCLK_SDIO_SAMPLE 157
+#define SCLK_VDU_CORE 158
+#define SCLK_VDU_CA 159
+#define SCLK_PCIE_PM 160
+#define SCLK_SPDIF_REC_DPTX 161
+#define SCLK_DPHY_PLL 162
+#define SCLK_DPHY_TX0_CFG 163
+#define SCLK_DPHY_TX1RX1_CFG 164
+#define SCLK_DPHY_RX0_CFG 165
+#define SCLK_RMII_SRC 166
+#define SCLK_PCIEPHY_REF100M 167
+#define SCLK_USBPHY0_480M_SRC 168
+#define SCLK_USBPHY1_480M_SRC 169
+#define SCLK_DDRCLK 170
+#define SCLK_TESTOUT2 171
+#define SCLK_UART0_SRC 172
+#define SCLK_UART_SRC 173
+#define SCLK_I2S0_DIV 174
+#define SCLK_I2S1_DIV 175
+#define SCLK_I2S2_DIV 176
+#define SCLK_SPDIF_DIV 177
+#define SCLK_I2S_8CH 178
+
+
+#define DCLK_VOP0 180
+#define DCLK_VOP1 181
+#define DCLK_VOP0_DIV 182
+#define DCLK_VOP1_DIV 183
+#define DCLK_M0_PERILP 184
+
+#define FCLK_CM0S 190
/* aclk gates */
#define ACLK_PERIHP 192
#define ACLK_GIC_ADB400_CORE_B_2_GIC 253
#define ACLK_GIC_ADB400_GIC_2_CORE_L 254
#define ACLK_GIC_ADB400_GIC_2_CORE_B 255
+#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
+#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
+#define ACLK_ADB400M_PD_CORE_L 258
+#define ACLK_ADB400M_PD_CORE_B 259
+#define ACLK_PERF_CORE_L 260
+#define ACLK_PERF_CORE_B 261
+#define ACLK_GIC_PRE 262
+#define ACLK_VOP0_PRE 263
+#define ACLK_VOP1_PRE 264
/* pclk gates */
#define PCLK_PERIHP 320
#define PCLK_EFUSE1024S 382
#define PCLK_PMU_INTR_ARB 383
#define PCLK_MAILBOX0 384
+#define PCLK_USBPHY_MUX_G 385
+#define PCLK_UPHY0_TCPHY_G 386
+#define PCLK_UPHY0_TCPD_G 387
+#define PCLK_UPHY1_TCPHY_G 388
+#define PCLK_UPHY1_TCPD_G 389
+#define PCLK_ALIVE 390
/* hclk gates */
#define HCLK_PERIHP 448
#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
/* pmu-clocks indices */
-#define SCLK_32K_SUSPEND_PMU 521
-#define SCLK_SPI3_PMU 522
-#define SCLK_TIMER12_PMU 523
-#define SCLK_TIMER13_PMU 524
-#define SCLK_UART4_PMU 525
-#define SCLK_PVTM_PMU 526
-#define SCLK_WIFI_PMU 527
-#define SCLK_I2C0_PMU 528
-#define SCLK_I2C4_PMU 529
-#define SCLK_I2C8_PMU 530
-
-#define PCLK_PMU 540
-#define PCLK_PMUGRF_PMU 541
-#define PCLK_INTMEM1_PMU 542
-#define PCLK_GPIO0_PMU 543
-#define PCLK_GPIO1_PMU 544
-#define PCLK_SGRF_PMU 545
-#define PCLK_NOC_PMU 546
-#define PCLK_I2C0_PMU 547
-#define PCLK_I2C4_PMU 548
-#define PCLK_I2C8_PMU 549
-#define PCLK_RKPWM_PMU 550
-#define PCLK_SPI3_PMU 551
-#define PCLK_TIMER_PMU 552
-#define PCLK_MAILBOX_PMU 553
-#define PCLK_UART4_PMU 554
-#define PCLK_WDT_M0_PMU 555
-
-#define FCLK_CM0S_PMU 560
-#define SCLK_CM0S_PMU 561
-#define HCLK_CM0S_PMU 562
-#define DCLK_CM0S_PMU 563
-#define PCLK_INTR_ARB_PMU 564
-#define HCLK_NOC_PMU 565
-
-#define CLKPMU_NR_CLKS (HCLK_NOC_PMU - SCLK_32K_SUSPEND_PMU + 1)
+
+#define PLL_PPLL 1
+
+#define SCLK_32K_SUSPEND_PMU 2
+#define SCLK_SPI3_PMU 3
+#define SCLK_TIMER12_PMU 4
+#define SCLK_TIMER13_PMU 5
+#define SCLK_UART4_PMU 6
+#define SCLK_PVTM_PMU 7
+#define SCLK_WIFI_PMU 8
+#define SCLK_I2C0_PMU 9
+#define SCLK_I2C4_PMU 10
+#define SCLK_I2C8_PMU 11
+
+#define PCLK_SRC_PMU 19
+#define PCLK_PMU 20
+#define PCLK_PMUGRF_PMU 21
+#define PCLK_INTMEM1_PMU 22
+#define PCLK_GPIO0_PMU 23
+#define PCLK_GPIO1_PMU 24
+#define PCLK_SGRF_PMU 25
+#define PCLK_NOC_PMU 26
+#define PCLK_I2C0_PMU 27
+#define PCLK_I2C4_PMU 28
+#define PCLK_I2C8_PMU 29
+#define PCLK_RKPWM_PMU 30
+#define PCLK_SPI3_PMU 31
+#define PCLK_TIMER_PMU 32
+#define PCLK_MAILBOX_PMU 33
+#define PCLK_UART4_PMU 34
+#define PCLK_WDT_M0_PMU 35
+
+#define FCLK_CM0S_SRC_PMU 44
+#define FCLK_CM0S_PMU 45
+#define SCLK_CM0S_PMU 46
+#define HCLK_CM0S_PMU 47
+#define DCLK_CM0S_PMU 48
+#define PCLK_INTR_ARB_PMU 49
+#define HCLK_NOC_PMU 50
+
+#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
/* soft-reset indices */
#define SRST_P_SPI0 214
#define SRST_P_SPI1 215
#define SRST_P_SPI2 216
-#define SRST_P_SPI3 217
-#define SRST_P_SPI4 218
+#define SRST_P_SPI4 217
+#define SRST_P_SPI5 218
#define SRST_SPI0 219
#define SRST_SPI1 220
#define SRST_SPI2 221
-#define SRST_SPI3 222
-#define SRST_SPI4 223
+#define SRST_SPI4 222
+#define SRST_SPI5 223
/* cru_softrst_con14 */
#define SRST_I2S0_8CH 224
#define SRST_P_EDP_CTRL 285
/* cru_softrst_con18 */
+#define SRST_A_GPU 288
#define SRST_A_GPU_NOC 289
#define SRST_A_GPU_GRF 290
#define SRST_PVTM_GPU 291
#define SRST_H_CM0S_NOC 3
#define SRST_DBG_CM0S 4
#define SRST_PO_CM0S 5
-#define SRST_P_SPI6 6
-#define SRST_SPI6 7
+#define SRST_P_SPI3 6
+#define SRST_SPI3 7
#define SRST_P_TIMER_0_1 8
#define SRST_P_TIMER_0 9
#define SRST_P_TIMER_1 10
projects / firefly-linux-kernel-4.4.55.git / blobdiff