Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...

[firefly-linux-kernel-4.4.55.git] / include / linux / clk-provider.h

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1f03528027949b61fe0897de5ddbe51d7165fbfe..11860985fecb90d156238d7f719f26540ea006b9 100644 (file)
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -249,9 +249,14 @@ struct clk_div_table {
  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
  *     register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
  *     the raw value read from the register, with the value of zero considered
- *     invalid
+ *     invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
  *     the hardware register
+ * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
+ *     CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
+ *     Some hardware implementations gracefully handle this case and allow a
+ *     zero divisor by not modifying their input clock
+ *     (divide by one / bypass).
  */
 struct clk_divider {
        struct clk_hw   hw;
@@ -265,6 +270,7 @@ struct clk_divider {
 
 #define CLK_DIVIDER_ONE_BASED          BIT(0)
 #define CLK_DIVIDER_POWER_OF_TWO       BIT(1)
+#define CLK_DIVIDER_ALLOW_ZERO         BIT(2)
 
 extern const struct clk_ops clk_divider_ops;
 struct clk *clk_register_divider(struct device *dev, const char *name,
@@ -284,7 +290,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
  * @reg:       register controlling multiplexer
  * @shift:     shift to multiplexer bit field
  * @width:     width of mutliplexer bit field
- * @num_clks:  number of parent clocks
+ * @flags:     hardware-specific flags
  * @lock:      register lock
  *
  * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
@@ -319,6 +325,8 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
                void __iomem *reg, u8 shift, u32 mask,
                u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 
+void of_fixed_factor_clk_setup(struct device_node *node);
+
 /**
  * struct clk_fixed_factor - fixed multiplier and divider clock
  *
@@ -346,11 +354,11 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
  * struct clk_composite - aggregate clock of mux, divider and gate clocks
  *
  * @hw:                handle between common and hardware-specific interfaces
- * @mux_hw:    handle between composite and hardware-specifix mux clock
- * @div_hw:    handle between composite and hardware-specifix divider clock
- * @gate_hw:   handle between composite and hardware-specifix gate clock
+ * @mux_hw:    handle between composite and hardware-specific mux clock
+ * @rate_hw:   handle between composite and hardware-specific rate clock
+ * @gate_hw:   handle between composite and hardware-specific gate clock
  * @mux_ops:   clock ops for mux
- * @div_ops:   clock ops for divider
+ * @rate_ops:  clock ops for rate
  * @gate_ops:  clock ops for gate
  */
 struct clk_composite {
@@ -358,18 +366,18 @@ struct clk_composite {
        struct clk_ops  ops;
 
        struct clk_hw   *mux_hw;
-       struct clk_hw   *div_hw;
+       struct clk_hw   *rate_hw;
        struct clk_hw   *gate_hw;
 
        const struct clk_ops    *mux_ops;
-       const struct clk_ops    *div_ops;
+       const struct clk_ops    *rate_ops;
        const struct clk_ops    *gate_ops;
 };
 
 struct clk *clk_register_composite(struct device *dev, const char *name,
                const char **parent_names, int num_parents,
                struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
-               struct clk_hw *div_hw, const struct clk_ops *div_ops,
+               struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
                struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
                unsigned long flags);