ARM64: dts: rockchip: enable tsadc node for rk3366-tb

[firefly-linux-kernel-4.4.55.git] / include / linux / mfd / rt5025-misc.h

diff --git a/include/linux/mfd/rt5025-misc.h b/include/linux/mfd/rt5025-misc.h
old mode 100644 (file)
new mode 100755 (executable)
index 20cadd2..8db2ab7
--- a/include/linux/mfd/rt5025-misc.h
+++ b/include/linux/mfd/rt5025-misc.h
@@ -1,5 +1,5 @@
 /*
- *  include/linux/mfd/rt5025-misc.h
+ *  include/linux/mfd/rt5025/rt5025-misc.h
  *  Include header file for Richtek RT5025 PMIC Misc
  *
  *  Copyright (C) 2013 Richtek Technology Corp.
@@ -14,15 +14,36 @@
 #ifndef __LINUX_RT5025_MISC_H
 #define __LINUX_RT5025_MISC_H
 
-#define RT5025_RESETCTRL_REG   0x15
-#define RT5025_VSYSULVO_REG    0x17
-#define RT5025_PWRONCTRL_REG   0x19
-#define RT5025_SHDNCTRL_REG    0x1A
-#define RT5025_PWROFFEN_REG    0x1B
-#define RT5025_CHENH_REG       0x62
-#define RT5025_CHENL_REG       0x63
+enum {
+       MISCEVENT_GPIO0_IE = 1,
+       MISCEVENT_GPIO1_IE,
+       MISCEVENT_GPIO2_IE,
+       MISCEVENT_RESETB,
+       MISCEVENT_PWRONF,
+       MISCEVENT_PWRONR,
+       MISCEVENT_KPSHDN,
+       MISCEVENT_SYSLV,
+       MISCEVENT_DCDC4LVHV,
+       MISCEVENT_PWRONLP_IRQ,
+       MISCEVENT_PWRONSP_IRQ,
+       MISCEVENT_DCDC3LV,
+       MISCEVENT_DCDC2LV,
+       MISCEVENT_DCDC1LV,
+       MISCEVENT_OT,
+       MISCEVENT_MAX,
+};
 
 #define RT5025_SHDNCTRL_MASK   0x80
 #define RT5025_VSYSOFF_MASK    0xE0
+#define RT5025_VSYSOFF_SHFT    5
+#define RT5025_SHDNLPRESS_MASK 0x0C
+#define RT5025_SHDNLPRESS_SHFT 2
+#define RT5025_STARTLPRESS_MASK        0xC0
+#define RT5025_STARTLPRESS_SHFT        6
+#define RT5025_VSYSLVSHDN_MASK 0x80
+#define RT5025_VSYSLVSHDN_SHFT 7
+#define RT5025_CABLEIN_MASK    0x03
+
+extern int rt5025_cable_exist(void);
 
 #endif /* #ifndef __LINUX_RT5025_MISC_H */