Merge branches 'x86-build-for-linus', 'x86-cleanups-for-linus' and 'x86-debug-for...

[firefly-linux-kernel-4.4.55.git] / include / linux / mtd / nand.h

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index c300db3ae2852b88321c618daeb10bdc4eb5b21b..e4d451e4600b1ac1fc66137202908d2b228f36a7 100644 (file)
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -587,6 +587,11 @@ struct nand_buffers {
  * @ecc_step_ds:       [INTERN] ECC step required by the @ecc_strength_ds,
  *                      also from the datasheet. It is the recommended ECC step
  *                     size, if known; if unknown, set to zero.
+ * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
+ *                           either deduced from the datasheet if the NAND
+ *                           chip is not ONFI compliant or set to 0 if it is
+ *                           (an ONFI chip is always configured in mode 0
+ *                           after a NAND reset)
  * @numchips:          [INTERN] number of physical chips
  * @chipsize:          [INTERN] the size of one chip for multichip arrays
  * @pagemask:          [INTERN] page number mask = number of (pages / chip) - 1
@@ -671,6 +676,7 @@ struct nand_chip {
        uint8_t bits_per_cell;
        uint16_t ecc_strength_ds;
        uint16_t ecc_step_ds;
+       int onfi_timing_mode_default;
        int badblockpos;
        int badblockbits;
 
@@ -766,12 +772,17 @@ struct nand_chip {
  * @options: stores various chip bit options
  * @id_len: The valid length of the @id.
  * @oobsize: OOB size
+ * @ecc: ECC correctability and step information from the datasheet.
  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
  *                   @ecc_strength_ds in nand_chip{}.
  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
  *               For example, the "4bit ECC for each 512Byte" can be set with
  *               NAND_ECC_INFO(4, 512).
+ * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
+ *                           reset. Should be deduced from timings described
+ *                           in the datasheet.
+ *
  */
 struct nand_flash_dev {
        char *name;
@@ -792,6 +803,7 @@ struct nand_flash_dev {
                uint16_t strength_ds;
                uint16_t step_ds;
        } ecc;
+       int onfi_timing_mode_default;
 };
 
 /**