#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
#define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Intrinsics.h"
-#include "llvm/IR/Type.h"
#include "llvm/Pass.h"
#include "llvm/Support/DataTypes.h"
namespace llvm {
+class GlobalValue;
+class Loop;
+class Type;
+class User;
+class Value;
+
/// TargetTransformInfo - This pass provides access to the codegen
/// interfaces that are needed for IR-level transformations.
class TargetTransformInfo {
/// fundamental values that should be used to interpret (and produce) those
/// costs. The costs are returned as an unsigned rather than a member of this
/// enumeration because it is expected that the cost of one IR instruction
- /// may have a multiplicative factor to it or otherwise won't fit dircetly
+ /// may have a multiplicative factor to it or otherwise won't fit directly
/// into the enum. Moreover, it is common to sum or average costs which works
/// better as simple integral values. Thus this enum only provides constants.
///
/// comments for a detailed explanation of the cost values.
virtual unsigned getUserCost(const User *U) const;
+ /// \brief hasBranchDivergence - Return true if branch divergence exists.
+ /// Branch divergence has a significantly negative impact on GPU performance
+ /// when threads in the same wavefront take different paths due to conditional
+ /// branches.
+ virtual bool hasBranchDivergence() const;
+
/// \brief Test whether calls to a function lower to actual program function
/// calls.
///
/// incurs significant execution cost.
virtual bool isLoweredToCall(const Function *F) const;
+ /// Parameters that control the generic loop unrolling transformation.
+ struct UnrollingPreferences {
+ /// The cost threshold for the unrolled loop, compared to
+ /// CodeMetrics.NumInsts aggregated over all basic blocks in the loop body.
+ /// The unrolling factor is set such that the unrolled loop body does not
+ /// exceed this cost. Set this to UINT_MAX to disable the loop body cost
+ /// restriction.
+ unsigned Threshold;
+ /// The cost threshold for the unrolled loop when optimizing for size (set
+ /// to UINT_MAX to disable).
+ unsigned OptSizeThreshold;
+ /// A forced unrolling factor (the number of concatenated bodies of the
+ /// original loop in the unrolled loop body). When set to 0, the unrolling
+ /// transformation will select an unrolling factor based on the current cost
+ /// threshold and other factors.
+ unsigned Count;
+ /// Allow partial unrolling (unrolling of loops to expand the size of the
+ /// loop body, not only to eliminate small constant-trip-count loops).
+ bool Partial;
+ /// Allow runtime unrolling (unrolling of loops to expand the size of the
+ /// loop body even when the number of loop iterations is not known at compile
+ /// time).
+ bool Runtime;
+ };
+
+ /// \brief Get target-customized preferences for the generic loop unrolling
+ /// transformation. The caller will initialize UP with the current
+ /// target-independent defaults.
+ virtual void getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const;
+
/// @}
/// \name Scalar Target Information
/// significantly boost the performance when the population is dense, and it
/// may or may not degrade performance if the population is sparse. A HW
/// support is considered as "Fast" if it can outperform, or is on a par
- /// with, SW implementaion when the population is sparse; otherwise, it is
+ /// with, SW implementation when the population is sparse; otherwise, it is
/// considered as "Slow".
enum PopcntSupportKind {
PSK_Software,
PSK_FastHardware
};
- /// isLegalAddImmediate - Return true if the specified immediate is legal
- /// add immediate, that is the target has add instructions which can add
- /// a register with the immediate without having to materialize the
- /// immediate into a register.
+ /// \brief Return true if the specified immediate is legal add immediate, that
+ /// is the target has add instructions which can add a register with the
+ /// immediate without having to materialize the immediate into a register.
virtual bool isLegalAddImmediate(int64_t Imm) const;
- /// isLegalICmpImmediate - Return true if the specified immediate is legal
- /// icmp immediate, that is the target has icmp instructions which can compare
- /// a register against the immediate without having to materialize the
- /// immediate into a register.
+ /// \brief Return true if the specified immediate is legal icmp immediate,
+ /// that is the target has icmp instructions which can compare a register
+ /// against the immediate without having to materialize the immediate into a
+ /// register.
virtual bool isLegalICmpImmediate(int64_t Imm) const;
- /// isLegalAddressingMode - Return true if the addressing mode represented by
- /// AM is legal for this target, for a load/store of the specified type.
+ /// \brief Return true if the addressing mode represented by AM is legal for
+ /// this target, for a load/store of the specified type.
/// The type may be VoidTy, in which case only return true if the addressing
/// mode is legal for a load/store of any legal type.
/// TODO: Handle pre/postinc as well.
int64_t BaseOffset, bool HasBaseReg,
int64_t Scale) const;
- /// isTruncateFree - Return true if it's free to truncate a value of
- /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
- /// register EAX to i16 by referencing its sub-register AX.
+ /// \brief Return the cost of the scaling factor used in the addressing
+ /// mode represented by AM for this target, for a load/store
+ /// of the specified type.
+ /// If the AM is supported, the return value must be >= 0.
+ /// If the AM is not supported, it returns a negative value.
+ /// TODO: Handle pre/postinc as well.
+ virtual int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
+ int64_t BaseOffset, bool HasBaseReg,
+ int64_t Scale) const;
+
+ /// \brief Return true if it's free to truncate a value of type Ty1 to type
+ /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
+ /// by referencing its sub-register AX.
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
- /// Is this type legal.
+ /// \brief Return true if this type is legal.
virtual bool isTypeLegal(Type *Ty) const;
- /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
+ /// \brief Returns the target's jmp_buf alignment in bytes.
virtual unsigned getJumpBufAlignment() const;
- /// getJumpBufSize - returns the target's jmp_buf size in bytes.
+ /// \brief Returns the target's jmp_buf size in bytes.
virtual unsigned getJumpBufSize() const;
- /// shouldBuildLookupTables - Return true if switches should be turned into
- /// lookup tables for the target.
+ /// \brief Return true if switches should be turned into lookup tables for the
+ /// target.
virtual bool shouldBuildLookupTables() const;
- /// getPopcntSupport - Return hardware support for population count.
+ /// \brief Return hardware support for population count.
virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
- /// getIntImmCost - Return the expected cost of materializing the given
- /// integer immediate of the specified type.
+ /// \brief Return true if the hardware has a fast square-root instruction.
+ virtual bool haveFastSqrt(Type *Ty) const;
+
+ /// \brief Return the expected cost of materializing for the given integer
+ /// immediate of the specified type.
virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
+ /// \brief Return the expected cost of materialization for the given integer
+ /// immediate of the specified type for a given instruction. The cost can be
+ /// zero if the immediate can be folded into the specified instruction.
+ virtual unsigned getIntImmCost(unsigned Opcode, const APInt &Imm,
+ Type *Ty) const;
+ virtual unsigned getIntImmCost(Intrinsic::ID IID, const APInt &Imm,
+ Type *Ty) const;
/// @}
/// \name Vector Target Information
SK_ExtractSubvector ///< ExtractSubvector Index indicates start offset.
};
+ /// \brief Additional information about an operand's possible values.
+ enum OperandValueKind {
+ OK_AnyValue, // Operand can have any value.
+ OK_UniformValue, // Operand is uniform (splat of a value).
+ OK_UniformConstantValue // Operand is uniform constant.
+ };
+
/// \return The number of scalar or vector registers that the target has.
/// If 'Vectors' is true, it returns the number of vector registers. If it is
/// set to false, it returns the number of scalar registers.
virtual unsigned getMaximumUnrollFactor() const;
/// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
- virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
+ virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
+ OperandValueKind Opd1Info = OK_AnyValue,
+ OperandValueKind Opd2Info = OK_AnyValue) const;
/// \return The cost of a shuffle instruction of kind Kind and of type Tp.
/// The index and subtype parameters are used by the subvector insertion and
virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
Type *Src) const;
- /// \return The expected cost of control-flow related instrutctions such as
+ /// \return The expected cost of control-flow related instructions such as
/// Phi, Ret, Br.
virtual unsigned getCFInstrCost(unsigned Opcode) const;
unsigned Alignment,
unsigned AddressSpace) const;
+ /// \brief Calculate the cost of performing a vector reduction.
+ ///
+ /// This is the cost of reducing the vector value of type \p Ty to a scalar
+ /// value using the operation denoted by \p Opcode. The form of the reduction
+ /// can either be a pairwise reduction or a reduction that splits the vector
+ /// at every reduction level.
+ ///
+ /// Pairwise:
+ /// (v0, v1, v2, v3)
+ /// ((v0+v1), (v2, v3), undef, undef)
+ /// Split:
+ /// (v0, v1, v2, v3)
+ /// ((v0+v2), (v1+v3), undef, undef)
+ virtual unsigned getReductionCost(unsigned Opcode, Type *Ty,
+ bool IsPairwiseForm) const;
+
/// \returns The cost of Intrinsic instructions.
virtual unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
ArrayRef<Type *> Tys) const;
/// split during legalization. Zero is returned when the answer is unknown.
virtual unsigned getNumberOfParts(Type *Tp) const;
+ /// \returns The cost of the address computation. For most targets this can be
+ /// merged into the instruction indexing mode. Some targets might want to
+ /// distinguish between address computation for memory operations on vector
+ /// types and scalar types. Such targets should override this function.
+ /// The 'IsComplex' parameter is a hint that the address computation is likely
+ /// to involve multiple instructions and as such unlikely to be merged into
+ /// the address indexing mode.
+ virtual unsigned getAddressComputationCost(Type *Ty,
+ bool IsComplex = false) const;
+
/// @}
/// Analysis group identification.
/// \brief Create the base case instance of a pass in the TTI analysis group.
///
-/// This class provides the base case for the stack of TTI analyses. It doesn't
+/// This class provides the base case for the stack of TTI analyzes. It doesn't
/// delegate to anything and uses the STTI and VTTI objects passed in to
/// satisfy the queries.
ImmutablePass *createNoTargetTransformInfoPass();
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