improve comments.

[oota-llvm.git] / include / llvm / CodeGen / FastISel.h

diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index 085810aaf116cae2d6e9b4f25754df00a1feccd5..857267c0112e388e061c30e7ff4a0f7bf8ad0a44 100644 (file)
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -16,7 +16,6 @@
 
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallSet.h"
-#include "llvm/CodeGen/DebugLoc.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 
 namespace llvm {
@@ -61,6 +60,7 @@ protected:
   const TargetData &TD;
   const TargetInstrInfo &TII;
   const TargetLowering &TLI;
+  LLVMContext *Context;
 
 public:
   /// startNewBlock - Set the current block to which generated machine
@@ -83,6 +83,9 @@ public:
   ///
   void setCurDebugLoc(DebugLoc dl) { DL = dl; }
 
+  /// getCurDebugLoc() - Return current debug location information.
+  DebugLoc getCurDebugLoc() const { return DL; }
+
   /// SelectInstruction - Do "fast" instruction selection for the given
   /// LLVM IR instruction, and append generated machine instructions to
   /// the current block. Return true if selection was successful.
@@ -279,7 +282,7 @@ protected:
   /// the CFG.
   void FastEmitBranch(MachineBasicBlock *MBB);
 
-  void UpdateValueMap(Value* I, unsigned Reg);
+  unsigned UpdateValueMap(Value* I, unsigned Reg);
 
   unsigned createResultReg(const TargetRegisterClass *RC);