#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/Target/TargetLowering.h"
namespace llvm {
unsigned NumFixedArgs;
CallingConv::ID CallConv;
const Value *Callee;
- const char *SymName;
+ MCSymbol *Symbol;
ArgListTy Args;
ImmutableCallSite *CS;
MachineInstr *Call;
unsigned ResultReg;
unsigned NumResultRegs;
+ bool IsPatchPoint;
+
SmallVector<Value *, 16> OutVals;
SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
SmallVector<unsigned, 16> OutRegs;
: RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
- Callee(nullptr), SymName(nullptr), CS(nullptr), Call(nullptr),
- ResultReg(0), NumResultRegs(0) {}
+ Callee(nullptr), Symbol(nullptr), CS(nullptr), Call(nullptr),
+ ResultReg(0), NumResultRegs(0), IsPatchPoint(false) {}
CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
const Value *Target, ArgListTy &&ArgsList,
RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
CallConv = Call.getCallingConv();
- NumFixedArgs = FuncTy->getNumParams();
Args = std::move(ArgsList);
+ NumFixedArgs = FuncTy->getNumParams();
CS = &Call;
}
CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
- const char *Target, ArgListTy &&ArgsList,
+ MCSymbol *Target, ArgListTy &&ArgsList,
ImmutableCallSite &Call,
unsigned FixedArgs = ~0U) {
RetTy = ResultTy;
Callee = Call.getCalledValue();
- SymName = Target;
+ Symbol = Target;
IsInReg = Call.paramHasAttr(0, Attribute::InReg);
DoesNotReturn = Call.doesNotReturn();
RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
CallConv = Call.getCallingConv();
- NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
Args = std::move(ArgsList);
+ NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
CS = &Call;
RetTy = ResultTy;
Callee = Target;
CallConv = CC;
+ Args = std::move(ArgsList);
NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
+ return *this;
+ }
+
+ CallLoweringInfo &setCallee(const DataLayout &DL, MCContext &Ctx,
+ CallingConv::ID CC, Type *ResultTy,
+ const char *Target, ArgListTy &&ArgsList,
+ unsigned FixedArgs = ~0U);
+
+ CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
+ MCSymbol *Target, ArgListTy &&ArgsList,
+ unsigned FixedArgs = ~0U) {
+ RetTy = ResultTy;
+ Symbol = Target;
+ CallConv = CC;
Args = std::move(ArgsList);
+ NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
return *this;
}
return *this;
}
+ CallLoweringInfo &setIsPatchPoint(bool Value = true) {
+ IsPatchPoint = Value;
+ return *this;
+ }
+
ArgListTy &getArgs() { return Args; }
void clearOuts() {
const TargetRegisterClass *RC, unsigned Op0,
bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
- /// \brief Emit a MachineInstr with two register operands and a result
+ /// \brief Emit a MachineInstr with a floating point immediate, and a result
/// register in the given register class.
- unsigned fastEmitInst_rf(unsigned MachineInstOpcode,
- const TargetRegisterClass *RC, unsigned Op0,
- bool Op0IsKill, const ConstantFP *FPImm);
+ unsigned fastEmitInst_f(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC,
+ const ConstantFP *FPImm);
/// \brief Emit a MachineInstr with two register operands, an immediate, and a
/// result register in the given register class.
bool Op0IsKill, unsigned Op1, bool Op1IsKill,
uint64_t Imm);
- /// \brief Emit a MachineInstr with two register operands, two immediates
- /// operands, and a result register in the given register class.
- unsigned fastEmitInst_rrii(unsigned MachineInstOpcode,
- const TargetRegisterClass *RC, unsigned Op0,
- bool Op0IsKill, unsigned Op1, bool Op1IsKill,
- uint64_t Imm1, uint64_t Imm2);
-
/// \brief Emit a MachineInstr with a single immediate operand, and a result
/// register in the given register class.
unsigned fastEmitInst_i(unsigned MachineInstrOpcode,
const TargetRegisterClass *RC, uint64_t Imm);
- /// \brief Emit a MachineInstr with a two immediate operands.
- unsigned fastEmitInst_ii(unsigned MachineInstrOpcode,
- const TargetRegisterClass *RC, uint64_t Imm1,
- uint64_t Imm2);
-
/// \brief Emit a MachineInstr for an extract_subreg from a specified index of
/// a superregister to a specified type.
unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
/// immediate (fall-through) successor, and update the CFG.
void fastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
+ /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
+ /// and adds TrueMBB and FalseMBB to the successor list.
+ void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB,
+ MachineBasicBlock *FalseMBB);
+
/// \brief Update the value map to include the new mapping for this
/// instruction, or insert an extra copy to get the result in a previous
/// determined register.
/// \brief Create a machine mem operand from the given instruction.
MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
- bool lowerCallTo(const CallInst *CI, const char *SymName, unsigned NumArgs);
+ CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
+
+ bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
+ bool lowerCallTo(const CallInst *CI, const char *SymbolName,
+ unsigned NumArgs);
bool lowerCallTo(CallLoweringInfo &CLI);
bool isCommutativeIntrinsic(IntrinsicInst const *II) {