#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
#define LLVM_CODEGEN_INSTR_SCHEDULING_H
-class Pass;
+class FunctionPass;
class TargetMachine;
//---------------------------------------------------------------------------
// are still in SSA form.
//---------------------------------------------------------------------------
-Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &Target);
-
-
-//---------------------------------------------------------------------------
-// Function: ScheduleInstructions
-//
-// Purpose:
-// Entry point for instruction scheduling on machine code.
-// Schedules the machine instructions generated by instruction selection.
-// Assumes that register allocation has been done.
-//---------------------------------------------------------------------------
-
-// Not implemented yet.
-//bool ScheduleInstructions(Method *M, const TargetMachine &Target);
+FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &Target);
#endif