Rename getEntryNode -> getEntryBlock()

[oota-llvm.git] / include / llvm / CodeGen / InstrScheduling.h

diff --git a/include/llvm/CodeGen/InstrScheduling.h b/include/llvm/CodeGen/InstrScheduling.h
index dbe9211dca51b2d4ba9be77aea9b180781aaed12..1e9c0dcf500157cb8378e535865048b9a9fb815e 100644 (file)
--- a/include/llvm/CodeGen/InstrScheduling.h
+++ b/include/llvm/CodeGen/InstrScheduling.h
@@ -1,49 +1,18 @@
-// $Id$
-//***************************************************************************
-// File:
-//     InstrScheduling.h
-// 
-// Purpose:
-//     
-// History:
-//     7/23/01  -  Vikram Adve  -  Created
-//***************************************************************************
+//===-- InstrScheduling.h - Interface To Instruction Scheduling --*- C++ -*-==//
+//
+// This file defines a minimal, but complete, interface to instruction
+// scheduling.
+//
+//===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
 #define LLVM_CODEGEN_INSTR_SCHEDULING_H
 
-
-//************************ User Include Files *****************************/
-
-#include "llvm/Support/CommandLine.h"
-#include "llvm/CodeGen/TargetMachine.h"
-
-//************************ Opaque Declarations*****************************/
-
-class Method;
-class SchedulingManager;
-
-//************************ Exported Data Types *****************************/
-
-// Debug option levels for instruction scheduling
-enum SchedDebugLevel_t {
-  Sched_NoDebugInfo,
-  Sched_PrintMachineCode, 
-  Sched_PrintSchedTrace,
-  Sched_PrintSchedGraphs,
-};
-
-extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
-
-
-//************************** External Classes ******************************/
-
-
-//************************* External Functions *****************************/
-
+class FunctionPass;
+class TargetMachine;
 
 //---------------------------------------------------------------------------
-// Function: ScheduleInstructionsWithSSA
+// Function: createScheduleInstructionsWithSSAPass(..)
 // 
 // Purpose:
 //   Entry point for instruction scheduling on SSA form.
@@ -52,35 +21,6 @@ extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
 //   are still in SSA form.
 //---------------------------------------------------------------------------
 
-bool           ScheduleInstructionsWithSSA     (Method* method,
-                                                const TargetMachine &Target);
-
-
-//---------------------------------------------------------------------------
-// Function: ScheduleInstructions
-// 
-// Purpose:
-//   Entry point for instruction scheduling on machine code.
-//   Schedules the machine instructions generated by instruction selection.
-//   Assumes that register allocation has been done.
-//---------------------------------------------------------------------------
-
-// Not implemented yet.
-bool           ScheduleInstructions            (Method* method,
-                                                const TargetMachine &Target);
-
-//---------------------------------------------------------------------------
-// Function: instrIsFeasible
-// 
-// Purpose:
-//   Used by the priority analysis to filter out instructions
-//   that are not feasible to issue in the current cycle.
-//   Should only be used during schedule construction..
-//---------------------------------------------------------------------------
-
-bool           instrIsFeasible                 (const SchedulingManager& S,
-                                                MachineOpCode opCode);
-
-//**************************************************************************/
+FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &Target);
 
 #endif