-// $Id$ -*- C++ -*-
-//***************************************************************************
-// File:
-// InstrScheduling.h
-//
-// Purpose:
-//
-// History:
-// 7/23/01 - Vikram Adve - Created
-//***************************************************************************
+//===-- InstrScheduling.h - Interface To Instruction Scheduling --*- C++ -*-==//
+//
+// This file defines a minimal, but complete, interface to instruction
+// scheduling.
+//
+//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
#define LLVM_CODEGEN_INSTR_SCHEDULING_H
-#include "llvm/CodeGen/MachineInstr.h"
-
-class Method;
-class SchedulingManager;
+class FunctionPass;
class TargetMachine;
-class MachineSchedInfo;
//---------------------------------------------------------------------------
-// Function: ScheduleInstructionsWithSSA
+// Function: createScheduleInstructionsWithSSAPass(..)
//
// Purpose:
// Entry point for instruction scheduling on SSA form.
// are still in SSA form.
//---------------------------------------------------------------------------
-bool ScheduleInstructionsWithSSA(Method *M, const TargetMachine &Target);
-
-
-//---------------------------------------------------------------------------
-// Function: ScheduleInstructions
-//
-// Purpose:
-// Entry point for instruction scheduling on machine code.
-// Schedules the machine instructions generated by instruction selection.
-// Assumes that register allocation has been done.
-//---------------------------------------------------------------------------
-
-// Not implemented yet.
-bool ScheduleInstructions (Method* method,
- const TargetMachine &Target);
-
-//---------------------------------------------------------------------------
-// Function: instrIsFeasible
-//
-// Purpose:
-// Used by the priority analysis to filter out instructions
-// that are not feasible to issue in the current cycle.
-// Should only be used during schedule construction..
-//---------------------------------------------------------------------------
+FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &Target);
-bool instrIsFeasible (const SchedulingManager& S,
- MachineOpCode opCode);
#endif