Register scavenger is now capable of scavenging. It spills a register whose use of...

[oota-llvm.git] / include / llvm / CodeGen / InstrScheduling.h

diff --git a/include/llvm/CodeGen/InstrScheduling.h b/include/llvm/CodeGen/InstrScheduling.h
index 40ce442f552fa52025a3a8b7d5c7f88b926f0fe4..c9aee2244a6b89b02d217d9bb9e858045c0c7796 100644 (file)
--- a/include/llvm/CodeGen/InstrScheduling.h
+++ b/include/llvm/CodeGen/InstrScheduling.h
@@ -1,10 +1,10 @@
 //===-- InstrScheduling.h - Interface To Instruction Scheduling -*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines a minimal, but complete, interface to instruction
@@ -15,12 +15,14 @@
 #ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
 #define LLVM_CODEGEN_INSTR_SCHEDULING_H
 
+namespace llvm {
+
 class FunctionPass;
 class TargetMachine;
 
 //---------------------------------------------------------------------------
 // Function: createScheduleInstructionsWithSSAPass(..)
-// 
+//
 // Purpose:
 //   Entry point for instruction scheduling on SSA form.
 //   Schedules the machine instructions generated by instruction selection.
@@ -30,4 +32,6 @@ class TargetMachine;
 
 FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &TM);
 
+} // End llvm namespace
+
 #endif