Register scavenger is now capable of scavenging. It spills a register whose use of...

[oota-llvm.git] / include / llvm / CodeGen / InstrScheduling.h

diff --git a/include/llvm/CodeGen/InstrScheduling.h b/include/llvm/CodeGen/InstrScheduling.h
index 8f88a61590a14dbdb9cf9e8c06f3692cd6acae0f..c9aee2244a6b89b02d217d9bb9e858045c0c7796 100644 (file)
--- a/include/llvm/CodeGen/InstrScheduling.h
+++ b/include/llvm/CodeGen/InstrScheduling.h
@@ -1,40 +1,28 @@
-// $Id$ -*- C++ -*-
-//***************************************************************************
-// File:
-//     InstrScheduling.h
-// 
-// Purpose:
-//     
-// History:
-//     7/23/01  -  Vikram Adve  -  Created
-//***************************************************************************
+//===-- InstrScheduling.h - Interface To Instruction Scheduling -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines a minimal, but complete, interface to instruction
+// scheduling.
+//
+//===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
 #define LLVM_CODEGEN_INSTR_SCHEDULING_H
 
-#include "llvm/Support/CommandLine.h"
-#include "llvm/CodeGen/MachineInstr.h"
+namespace llvm {
 
-class Method;
-class SchedulingManager;
+class FunctionPass;
 class TargetMachine;
-class MachineSchedInfo;
-
-// Debug option levels for instruction scheduling
-enum SchedDebugLevel_t {
-  Sched_NoDebugInfo,
-  Sched_PrintMachineCode, 
-  Sched_PrintSchedTrace,
-  Sched_PrintSchedGraphs,
-};
-
-extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
-
-
 
 //---------------------------------------------------------------------------
-// Function: ScheduleInstructionsWithSSA
-// 
+// Function: createScheduleInstructionsWithSSAPass(..)
+//
 // Purpose:
 //   Entry point for instruction scheduling on SSA form.
 //   Schedules the machine instructions generated by instruction selection.
@@ -42,31 +30,8 @@ extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
 //   are still in SSA form.
 //---------------------------------------------------------------------------
 
-bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &Target);
-
+FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &TM);
 
-//---------------------------------------------------------------------------
-// Function: ScheduleInstructions
-// 
-// Purpose:
-//   Entry point for instruction scheduling on machine code.
-//   Schedules the machine instructions generated by instruction selection.
-//   Assumes that register allocation has been done.
-//---------------------------------------------------------------------------
-
-// Not implemented yet.
-bool           ScheduleInstructions            (Method* method,
-                                                const TargetMachine &Target);
-
-//---------------------------------------------------------------------------
-// Function: instrIsFeasible
-// 
-// Purpose:
-//   Used by the priority analysis to filter out instructions
-//   that are not feasible to issue in the current cycle.
-//   Should only be used during schedule construction..
-//---------------------------------------------------------------------------
+} // End llvm namespace
 
-bool           instrIsFeasible                 (const SchedulingManager& S,
-                                                MachineOpCode opCode);
 #endif