-// $Id$
-//***************************************************************************
-// File:
-// InstrScheduling.h
-//
-// Purpose:
-//
-// History:
-// 7/23/01 - Vikram Adve - Created
-//***************************************************************************
+//===-- InstrScheduling.h - Interface To Instruction Scheduling -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines a minimal, but complete, interface to instruction
+// scheduling.
+//
+//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
#define LLVM_CODEGEN_INSTR_SCHEDULING_H
+namespace llvm {
-//************************ User Include Files *****************************/
-
-#include "llvm/Support/CommandLine.h"
-#include "llvm/CodeGen/TargetMachine.h"
-
-//************************ Opaque Declarations*****************************/
-
-class Method;
-class SchedulingManager;
-
-//************************ Exported Data Types *****************************/
-
-// Debug option levels for instruction scheduling
-enum SchedDebugLevel_t {
- Sched_NoDebugInfo,
- Sched_PrintMachineCode,
- Sched_PrintSchedTrace,
- Sched_PrintSchedGraphs,
-};
-
-extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
-
-
-//************************** External Classes ******************************/
-
-
-//************************* External Functions *****************************/
-
+class FunctionPass;
+class TargetMachine;
//---------------------------------------------------------------------------
-// Function: ScheduleInstructionsWithSSA
-//
+// Function: createScheduleInstructionsWithSSAPass(..)
+//
// Purpose:
// Entry point for instruction scheduling on SSA form.
// Schedules the machine instructions generated by instruction selection.
// are still in SSA form.
//---------------------------------------------------------------------------
-bool ScheduleInstructionsWithSSA (Method* method,
- const TargetMachine &Target);
-
-
-//---------------------------------------------------------------------------
-// Function: ScheduleInstructions
-//
-// Purpose:
-// Entry point for instruction scheduling on machine code.
-// Schedules the machine instructions generated by instruction selection.
-// Assumes that register allocation has been done.
-//---------------------------------------------------------------------------
-
-// Not implemented yet.
-bool ScheduleInstructions (Method* method,
- const TargetMachine &Target);
-
-//---------------------------------------------------------------------------
-// Function: instrIsFeasible
-//
-// Purpose:
-// Used by the priority analysis to filter out instructions
-// that are not feasible to issue in the current cycle.
-// Should only be used during schedule construction..
-//---------------------------------------------------------------------------
-
-bool instrIsFeasible (const SchedulingManager& S,
- MachineOpCode opCode);
+FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &TM);
-//**************************************************************************/
+} // End llvm namespace
#endif