Add missing const qualifiers.

[oota-llvm.git] / include / llvm / CodeGen / LiveIntervalAnalysis.h

diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h
index 717063ecff4b0a0b214dcf3df054df1a5db6fb36..10f60f4f05c156c8e9ecf6f82c682388e65770b5 100644 (file)
--- a/include/llvm/CodeGen/LiveIntervalAnalysis.h
+++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h
@@ -20,15 +20,18 @@
 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
 
-#include "llvm/ADT/DenseMap.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/IndexedMap.h"
 
 namespace llvm {
 
   class LiveVariables;
   class MRegisterInfo;
   class TargetInstrInfo;
+  class TargetRegisterClass;
   class VirtRegMap;
 
   class LiveIntervals : public MachineFunctionPass {
@@ -51,12 +54,20 @@ namespace llvm {
     typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
     Reg2IntervalMap r2iMap_;
 
-    typedef DenseMap<unsigned> Reg2RegMap;
+    typedef IndexedMap<unsigned> Reg2RegMap;
     Reg2RegMap r2rMap_;
 
-    std::vector<bool> allocatableRegs_;
+    BitVector allocatableRegs_;
+    DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
+
+    /// JoinedLIs - Keep track which register intervals have been coalesced
+    /// with other intervals.
+    BitVector JoinedLIs;
 
   public:
+    static char ID; // Pass identification, replacement for typeid
+    LiveIntervals() : MachineFunctionPass((intptr_t)&ID) {}
+
     struct CopyRec {
       MachineInstr *MI;
       unsigned SrcReg, DstReg;
@@ -117,6 +128,10 @@ namespace llvm {
       return I->second;
     }
 
+    bool hasInterval(unsigned reg) const {
+      return r2iMap_.count(reg);
+    }
+
     /// getMBBStartIdx - Return the base index of the first instruction in the
     /// specified MachineBasicBlock.
     unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
@@ -148,6 +163,11 @@ namespace llvm {
                                                      VirtRegMap& vrm,
                                                      int slot);
 
+    /// CreateNewLiveInterval - Create a new live interval with the given live
+    /// ranges. The new live interval will have an infinite spill weight.
+    LiveInterval &CreateNewLiveInterval(const LiveInterval *LI,
+                                        const std::vector<LiveRange> &LRs);
+
     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
     virtual void releaseMemory();
 
@@ -156,8 +176,17 @@ namespace llvm {
 
     /// print - Implement the dump method.
     virtual void print(std::ostream &O, const Module* = 0) const;
+    void print(std::ostream *O, const Module* M = 0) const {
+      if (O) print(*O, M);
+    }
 
   private:
+    /// isRemoved - returns true if the specified machine instr has been
+    /// removed.
+    bool isRemoved(MachineInstr* instr) const {
+      return !mi2iMap_.count(instr);
+    }
+
     /// RemoveMachineInstrFromMaps - This marks the specified machine instr as
     /// deleted.
     void RemoveMachineInstrFromMaps(MachineInstr *MI) {
@@ -179,14 +208,16 @@ namespace llvm {
     /// CopyCoallesceInMBB - Coallsece copies in the specified MBB, putting
     /// copies that cannot yet be coallesced into the "TryAgain" list.
     void CopyCoallesceInMBB(MachineBasicBlock *MBB,
-                            std::vector<CopyRec> &TryAgain);
+                         std::vector<CopyRec> *TryAgain, bool PhysOnly = false);
+
     /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
     /// which are the src/dst of the copy instruction CopyMI.  This returns true
     /// if the copy was successfully coallesced away, or if it is never possible
     /// to coallesce these this copy, due to register constraints.  It returns
     /// false if it is not currently possible to coallesce this interval, but
     /// it may be possible if other things get coallesced.
-    bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg);
+    bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg,
+                  bool PhysOnly = false);
     
     /// JoinIntervals - Attempt to join these two intervals.  On failure, this
     /// returns false.  Otherwise, if one of the intervals being joined is a
@@ -224,6 +255,11 @@ namespace llvm {
                                    LiveInterval &interval,
                                    unsigned SrcReg);
 
+    /// handleLiveInRegister - Create interval for a livein register.
+    void handleLiveInRegister(MachineBasicBlock* mbb,
+                              unsigned MIIdx,
+                              LiveInterval &interval, bool isAlias = false);
+
     /// Return true if the two specified registers belong to different
     /// register classes.  The registers may be either phys or virt regs.
     bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
@@ -232,11 +268,34 @@ namespace llvm {
     bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
                               MachineInstr *CopyMI);
 
-    bool overlapsAliases(const LiveInterval *lhs,
-                         const LiveInterval *rhs) const;
+    /// lastRegisterUse - Returns the last use of the specific register between
+    /// cycles Start and End. It also returns the use operand by reference. It
+    /// returns NULL if there are no uses.
+    MachineInstr *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
+                                  MachineOperand *&MOU);
+
+    /// findDefOperand - Returns the MachineOperand that is a def of the specific
+    /// register. It returns NULL if the def is not found.
+    MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg);
+
+    /// unsetRegisterKill - Unset IsKill property of all uses of the specific
+    /// register of the specific instruction.
+    void unsetRegisterKill(MachineInstr *MI, unsigned Reg);
+
+    /// unsetRegisterKills - Unset IsKill property of all uses of specific register
+    /// between cycles Start and End.
+    void unsetRegisterKills(unsigned Start, unsigned End, unsigned Reg);
+
+    /// hasRegisterDef - True if the instruction defines the specific register.
+    ///
+    bool hasRegisterDef(MachineInstr *MI, unsigned Reg);
 
     static LiveInterval createInterval(unsigned Reg);
 
+    void removeInterval(unsigned Reg) {
+      r2iMap_.erase(Reg);
+    }
+
     LiveInterval &getOrCreateInterval(unsigned reg) {
       Reg2IntervalMap::iterator I = r2iMap_.find(reg);
       if (I == r2iMap_.end())