#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Allocator.h"
#include <cmath>
-#include <map>
namespace llvm {
AliasAnalysis *aa_;
LiveVariables* lv_;
- /// AsmsWithEarlyClobber - maps a virtual register number to all the
- /// inline asm's that have the register marked earlyclobber.
- ///
- std::multimap<unsigned, MachineInstr*> AsmsThatEarlyClobber;
-
- /// AsmsWithEarlyClobberConflict - maps a virtual register number
- /// to all the inline asm's that have earlyclobber operands elsewhere
- /// and use the register as a (non-earlyclobber) input.
- ///
- /// Note: earlyclobber operands may not be assigned the same register as
- /// each other, or as earlyclobber-conflict operands. However two
- /// earlyclobber-conflict operands may be assigned the same register if
- /// they happen to contain the same value.
- ///
- std::multimap<unsigned, MachineInstr*> AsmsWithEarlyClobberConflict;
-
/// Special pool allocator for VNInfo's (LiveInterval val#).
///
BumpPtrAllocator VNInfoAllocator;
typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
Reg2IntervalMap r2iMap_;
+ DenseMap<MachineBasicBlock*, unsigned> terminatorGaps;
+
BitVector allocatableRegs_;
std::vector<MachineInstr*> ClonedMIs;
+ typedef LiveInterval::InstrSlots InstrSlots;
+
public:
static char ID; // Pass identification, replacement for typeid
LiveIntervals() : MachineFunctionPass(&ID) {}
- struct InstrSlots {
- enum {
- LOAD = 0,
- USE = 1,
- DEF = 2,
- STORE = 3,
- NUM = 4
- };
- };
-
static unsigned getBaseIndex(unsigned index) {
return index - (index % InstrSlots::NUM);
}
return i2miMap_[index];
}
+ /// hasGapBeforeInstr - Return true if the previous instruction slot,
+ /// i.e. Index - InstrSlots::NUM, is not occupied.
+ bool hasGapBeforeInstr(unsigned Index) {
+ Index = getBaseIndex(Index - InstrSlots::NUM);
+ return getInstructionFromIndex(Index) == 0;
+ }
+
+ /// hasGapAfterInstr - Return true if the successive instruction slot,
+ /// i.e. Index + InstrSlots::Num, is not occupied.
+ bool hasGapAfterInstr(unsigned Index) {
+ Index = getBaseIndex(Index + InstrSlots::NUM);
+ return getInstructionFromIndex(Index) == 0;
+ }
+
+ /// findGapBeforeInstr - Find an empty instruction slot before the
+ /// specified index. If "Furthest" is true, find one that's furthest
+ /// away from the index (but before any index that's occupied).
+ unsigned findGapBeforeInstr(unsigned Index, bool Furthest = false) {
+ Index = getBaseIndex(Index - InstrSlots::NUM);
+ if (getInstructionFromIndex(Index))
+ return 0; // No gap!
+ if (!Furthest)
+ return Index;
+ unsigned PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
+ while (getInstructionFromIndex(Index)) {
+ Index = PrevIndex;
+ PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
+ }
+ return Index;
+ }
+
+ /// InsertMachineInstrInMaps - Insert the specified machine instruction
+ /// into the instruction index map at the given index.
+ void InsertMachineInstrInMaps(MachineInstr *MI, unsigned Index) {
+ i2miMap_[Index / InstrSlots::NUM] = MI;
+ Mi2IndexMap::iterator it = mi2iMap_.find(MI);
+ assert(it == mi2iMap_.end() && "Already in map!");
+ mi2iMap_[MI] = Index;
+ }
+
/// conflictsWithPhysRegDef - Returns true if the specified register
/// is defined during the duration of the specified interval.
bool conflictsWithPhysRegDef(const LiveInterval &li, VirtRegMap &vrm,
unsigned reg);
+ /// conflictsWithPhysRegRef - Similar to conflictsWithPhysRegRef except
+ /// it can check use as well.
+ bool conflictsWithPhysRegRef(LiveInterval &li, unsigned Reg,
+ bool CheckUse,
+ SmallPtrSet<MachineInstr*,32> &JoinedCopies);
+
/// findLiveInMBBs - Given a live range, if the value of the range
/// is live in any MBB returns true as well as the list of basic blocks
/// in which the value is live.
- bool findLiveInMBBs(const LiveRange &LR,
+ bool findLiveInMBBs(unsigned Start, unsigned End,
+ SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
+
+ /// findReachableMBBs - Return a list MBB that can be reached via any
+ /// branch or fallthroughs. Return true if the list is not empty.
+ bool findReachableMBBs(unsigned Start, unsigned End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
// Interval creation
I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
return *I->second;
}
+
+ /// dupInterval - Duplicate a live interval. The caller is responsible for
+ /// managing the allocated memory.
+ LiveInterval *dupInterval(LiveInterval *li);
/// addLiveRangeToEndOfBlock - Given a register and an instruction,
/// adds a live range from that instruction to the end of its MBB.
r2iMap_.erase(I);
}
- /// isRemoved - returns true if the specified machine instr has been
- /// removed.
- bool isRemoved(MachineInstr* instr) const {
+ /// isNotInMIMap - returns true if the specified machine instr has been
+ /// removed or was never entered in the map.
+ bool isNotInMIMap(MachineInstr* instr) const {
return !mi2iMap_.count(instr);
}
/// (if any is created) by reference. This is temporary.
std::vector<LiveInterval*>
addIntervalsForSpills(const LiveInterval& i,
- const MachineLoopInfo *loopInfo, VirtRegMap& vrm,
- float &SSWeight);
+ SmallVectorImpl<LiveInterval*> &SpillIs,
+ const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
/// addIntervalsForSpillsFast - Quickly create new intervals for spilled
/// defs / uses without remat or splitting.
std::vector<LiveInterval*>
addIntervalsForSpillsFast(const LiveInterval &li,
- const MachineLoopInfo *loopInfo,
- VirtRegMap &vrm, float& SSWeight);
+ const MachineLoopInfo *loopInfo, VirtRegMap &vrm);
/// spillPhysRegAroundRegDefsUses - Spill the specified physical register
- /// around all defs and uses of the specified interval.
- void spillPhysRegAroundRegDefsUses(const LiveInterval &li,
+ /// around all defs and uses of the specified interval. Return true if it
+ /// was able to cut its interval.
+ bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
unsigned PhysReg, VirtRegMap &vrm);
/// isReMaterializable - Returns true if every definition of MI of every
/// val# of the specified interval is re-materializable. Also returns true
/// by reference if all of the defs are load instructions.
- bool isReMaterializable(const LiveInterval &li, bool &isLoad);
+ bool isReMaterializable(const LiveInterval &li,
+ SmallVectorImpl<LiveInterval*> &SpillIs,
+ bool &isLoad);
+
+ /// isReMaterializable - Returns true if the definition MI of the specified
+ /// val# of the specified interval is re-materializable.
+ bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
+ MachineInstr *MI);
/// getRepresentativeReg - Find the largest super register of the specified
/// physical register.
unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
unsigned PhysReg) const;
- /// noEarlyclobberConflict - see whether virtual reg VReg has a conflict
- /// with hard reg HReg because HReg is used as an earlyclobber register in
- /// asm that also has VReg live into or across it.
- bool noEarlyclobberConflict(unsigned VReg, VirtRegMap &vrm, unsigned HReg);
+ /// processImplicitDefs - Process IMPLICIT_DEF instructions. Add isUndef
+ /// marker to implicit_def defs and their uses.
+ void processImplicitDefs();
/// computeNumbering - Compute the index numbering.
void computeNumbering();
+ /// scaleNumbering - Rescale interval numbers to introduce gaps for new
+ /// instructions
+ void scaleNumbering(int factor);
+
+ /// intervalIsInOneMBB - Returns true if the specified interval is entirely
+ /// within a single basic block.
+ bool intervalIsInOneMBB(const LiveInterval &li) const;
+
private:
/// computeIntervals - Compute live intervals.
void computeIntervals();
/// val# of the specified interval is re-materializable. Also returns true
/// by reference if the def is a load.
bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
- MachineInstr *MI, bool &isLoad);
+ MachineInstr *MI,
+ SmallVectorImpl<LiveInterval*> &SpillIs,
+ bool &isLoad);
/// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
/// slot / to reg or any rematerialized load into ith operand of specified
bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
MachineBasicBlock *MBB, unsigned Idx) const;
- /// intervalIsInOneMBB - Returns true if the specified interval is entirely
- /// within a single basic block.
- bool intervalIsInOneMBB(const LiveInterval &li) const;
-
/// hasAllocatableSuperReg - Return true if the specified physical register
/// has any super register that's allocatable.
bool hasAllocatableSuperReg(unsigned Reg) const;
SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
DenseMap<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs, float &SSWeight);
+ std::vector<LiveInterval*> &NewLIs);
void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
LiveInterval::Ranges::const_iterator &I,
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
BitVector &RestoreMBBs,
DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
DenseMap<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs, float &SSWeight);
+ std::vector<LiveInterval*> &NewLIs);
static LiveInterval* createInterval(unsigned Reg);
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