// This file implements the LiveInterval analysis pass. Given some numbering of
// each the machine instructions (in this implemention depth-first order) an
// interval [i, j) is said to be a live interval for register v if there is no
-// instruction with number j' > j such that v is live at j' abd there is no
+// instruction with number j' > j such that v is live at j' and there is no
// instruction with number i' < i such that v is live at i'. In this
// implementation intervals can have holes, i.e. an interval might look like
// [1,20), [50,65), [1000,1001).
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Allocator.h"
#include <cmath>
+#include <map>
namespace llvm {
class VirtRegMap;
typedef std::pair<unsigned, MachineBasicBlock*> IdxMBBPair;
+ inline bool operator<(unsigned V, const IdxMBBPair &IM) {
+ return V < IM.first;
+ }
+
+ inline bool operator<(const IdxMBBPair &IM, unsigned V) {
+ return IM.first < V;
+ }
+
+ struct Idx2MBBCompare {
+ bool operator()(const IdxMBBPair &LHS, const IdxMBBPair &RHS) const {
+ return LHS.first < RHS.first;
+ }
+ };
+
class LiveIntervals : public MachineFunctionPass {
MachineFunction* mf_;
+ MachineRegisterInfo* mri_;
const TargetMachine* tm_;
const TargetRegisterInfo* tri_;
const TargetInstrInfo* tii_;
const_iterator end() const { return r2iMap_.end(); }
iterator begin() { return r2iMap_.begin(); }
iterator end() { return r2iMap_.end(); }
- unsigned getNumIntervals() const { return r2iMap_.size(); }
+ unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
LiveInterval &getInterval(unsigned reg) {
Reg2IntervalMap::iterator I = r2iMap_.find(reg);
return MBB2IdxMap[MBBNo].second;
}
+ /// getIntervalSize - get the size of an interval in "units,"
+ /// where every function is composed of one thousand units. This
+ /// measure scales properly with empty index slots in the function.
+ unsigned getScaledIntervalSize(LiveInterval& I) {
+ // Factor of 250 comes from 1000 units per function divided
+ // by four slots per instruction.
+ return (250 * I.getSize()) / i2miMap_.size();
+ }
+
+ /// getMBBFromIndex - given an index in any instruction of an
+ /// MBB return a pointer the MBB
+ MachineBasicBlock* getMBBFromIndex(unsigned index) const {
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), index);
+ // Take the pair containing the index
+ std::vector<IdxMBBPair>::const_iterator J =
+ ((I != Idx2MBBMap.end() && I->first > index) ||
+ (I == Idx2MBBMap.end() && Idx2MBBMap.size()>0)) ? (I-1): I;
+
+ assert(J != Idx2MBBMap.end() && J->first < index+1 &&
+ index <= getMBBEndIdx(J->second) &&
+ "index does not correspond to an MBB");
+ return J->second;
+ }
+
/// getInstructionIndex - returns the base index of instr
unsigned getInstructionIndex(MachineInstr* instr) const {
Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
return I->second;
}
+
+ /// addLiveRangeToEndOfBlock - Given a register and an instruction,
+ /// adds a live range from that instruction to the end of its MBB.
+ LiveRange addLiveRangeToEndOfBlock(unsigned reg,
+ MachineInstr* startInst);
// Interval removal
BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
+ /// getVNInfoSourceReg - Helper function that parses the specified VNInfo
+ /// copy field and returns the source register that defines it.
+ unsigned getVNInfoSourceReg(const VNInfo *VNI) const;
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual void releaseMemory();
}
/// addIntervalsForSpills - Create new intervals for spilled defs / uses of
- /// the given interval.
+ /// the given interval. FIXME: It also returns the weight of the spill slot
+ /// (if any is created) by reference. This is temporary.
std::vector<LiveInterval*>
addIntervalsForSpills(const LiveInterval& i,
- const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
+ const MachineLoopInfo *loopInfo, VirtRegMap& vrm,
+ float &SSWeight);
+
+ /// spillPhysRegAroundRegDefsUses - Spill the specified physical register
+ /// around all defs and uses of the specified interval.
+ void spillPhysRegAroundRegDefsUses(const LiveInterval &li,
+ unsigned PhysReg, VirtRegMap &vrm);
/// isReMaterializable - Returns true if every definition of MI of every
/// val# of the specified interval is re-materializable. Also returns true
/// by reference if all of the defs are load instructions.
bool isReMaterializable(const LiveInterval &li, bool &isLoad);
+ /// getRepresentativeReg - Find the largest super register of the specified
+ /// physical register.
+ unsigned getRepresentativeReg(unsigned Reg) const;
+
+ /// getNumConflictsWithPhysReg - Return the number of uses and defs of the
+ /// specified interval that conflicts with the specified physical register.
+ unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
+ unsigned PhysReg) const;
+
+ /// computeNumbering - Compute the index numbering.
+ void computeNumbering();
+
private:
/// computeIntervals - Compute live intervals.
void computeIntervals();
MachineBasicBlock::iterator mi,
unsigned MIIdx,
LiveInterval &interval,
- unsigned SrcReg);
+ MachineInstr *CopyMI);
/// handleLiveInRegister - Create interval for a livein register.
void handleLiveInRegister(MachineBasicBlock* mbb,
unsigned MIIdx,
LiveInterval &interval, bool isAlias = false);
+ /// getReMatImplicitUse - If the remat definition MI has one (for now, we
+ /// only allow one) virtual register operand, then its uses are implicitly
+ /// using the register. Returns the virtual register.
+ unsigned getReMatImplicitUse(const LiveInterval &li,
+ MachineInstr *MI) const;
+
+ /// isValNoAvailableAt - Return true if the val# of the specified interval
+ /// which reaches the given instruction also reaches the specified use
+ /// index.
+ bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
+ unsigned UseIdx) const;
+
/// isReMaterializable - Returns true if the definition MI of the specified
/// val# of the specified interval is re-materializable. Also returns true
/// by reference if the def is a load.
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg);
- /// canFoldMemoryOperand - Returns true if the specified load / store
+ /// canFoldMemoryOperand - Return true if the specified load / store
/// folding is possible.
bool canFoldMemoryOperand(MachineInstr *MI,
- SmallVector<unsigned, 2> &Ops) const;
+ SmallVector<unsigned, 2> &Ops,
+ bool ReMatLoadSS) const;
/// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
/// VNInfo that's after the specified index but is within the basic block.
/// within a single basic block.
bool intervalIsInOneMBB(const LiveInterval &li) const;
+ /// hasAllocatableSuperReg - Return true if the specified physical register
+ /// has any super register that's allocatable.
+ bool hasAllocatableSuperReg(unsigned Reg) const;
+
/// SRInfo - Spill / restore info.
struct SRInfo {
int index;
BitVector &RestoreMBBs,
std::map<unsigned,std::vector<SRInfo> >&RestoreIdxes);
+ /// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
+ /// spilled and create empty intervals for their uses.
+ void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
+ const TargetRegisterClass* rc,
+ std::vector<LiveInterval*> &NewLIs);
+
+ /// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
+ /// interval on to-be re-materialized operands of MI) with new register.
+ void rewriteImplicitOps(const LiveInterval &li,
+ MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
+
/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
/// functions for addIntervalsForSpills to rewrite uses / defs for the given
/// live range.
- bool rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
- unsigned id, unsigned index, unsigned end, MachineInstr *MI,
+ bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
+ bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
- VirtRegMap &vrm, MachineRegisterInfo &RegMap,
- const TargetRegisterClass* rc,
- SmallVector<int, 4> &ReMatIds,
- unsigned &NewVReg, bool &HasDef, bool &HasUse,
- const MachineLoopInfo *loopInfo,
+ VirtRegMap &vrm, const TargetRegisterClass* rc,
+ SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
+ unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
std::map<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs);
+ std::vector<LiveInterval*> &NewLIs, float &SSWeight);
void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
LiveInterval::Ranges::const_iterator &I,
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
- VirtRegMap &vrm, MachineRegisterInfo &RegMap,
- const TargetRegisterClass* rc,
+ VirtRegMap &vrm, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
BitVector &SpillMBBs,
std::map<unsigned,std::vector<SRInfo> > &SpillIdxes,
BitVector &RestoreMBBs,
std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes,
std::map<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs);
+ std::vector<LiveInterval*> &NewLIs, float &SSWeight);
static LiveInterval createInterval(unsigned Reg);
projects / oota-llvm.git / blobdiff