//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the LiveInterval analysis pass. Given some numbering of
// each the machine instructions (in this implemention depth-first order) an
// interval [i, j) is said to be a live interval for register v if there is no
-// instruction with number j' > j such that v is live at j' abd there is no
+// instruction with number j' > j such that v is live at j' and there is no
// instruction with number i' < i such that v is live at i'. In this
// implementation intervals can have holes, i.e. an interval might look like
// [1,20), [50,65), [1000,1001).
#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/Support/Allocator.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include <cmath>
+#include <iterator>
namespace llvm {
+ class AliasAnalysis;
+ class LiveRangeCalc;
class LiveVariables;
- class MRegisterInfo;
+ class MachineDominatorTree;
+ class MachineLoopInfo;
+ class TargetRegisterInfo;
+ class MachineRegisterInfo;
class TargetInstrInfo;
class TargetRegisterClass;
class VirtRegMap;
class LiveIntervals : public MachineFunctionPass {
- MachineFunction* mf_;
- const TargetMachine* tm_;
- const MRegisterInfo* mri_;
- const TargetInstrInfo* tii_;
- LiveVariables* lv_;
+ MachineFunction* MF;
+ MachineRegisterInfo* MRI;
+ const TargetMachine* TM;
+ const TargetRegisterInfo* TRI;
+ const TargetInstrInfo* TII;
+ AliasAnalysis *AA;
+ LiveVariables* LV;
+ SlotIndexes* Indexes;
+ MachineDominatorTree *DomTree;
+ LiveRangeCalc *LRCalc;
+
+ /// Special pool allocator for VNInfo's (LiveInterval val#).
+ ///
+ VNInfo::Allocator VNInfoAllocator;
- /// MBB2IdxMap - The index of the first instruction in the specified basic
+ /// Live interval pointers for all the virtual registers.
+ IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
+
+ /// RegMaskSlots - Sorted list of instructions with register mask operands.
+ /// Always use the 'r' slot, RegMasks are normal clobbers, not early
+ /// clobbers.
+ SmallVector<SlotIndex, 8> RegMaskSlots;
+
+ /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
+ /// pointer to the corresponding register mask. This pointer can be
+ /// recomputed as:
+ ///
+ /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
+ /// unsigned OpNum = findRegMaskOperand(MI);
+ /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
+ ///
+ /// This is kept in a separate vector partly because some standard
+ /// libraries don't support lower_bound() with mixed objects, partly to
+ /// improve locality when searching in RegMaskSlots.
+ /// Also see the comment in LiveInterval::find().
+ SmallVector<const uint32_t*, 8> RegMaskBits;
+
+ /// For each basic block number, keep (begin, size) pairs indexing into the
+ /// RegMaskSlots and RegMaskBits arrays.
+ /// Note that basic block numbers may not be layout contiguous, that's why
+ /// we can't just keep track of the first register mask in each basic
/// block.
- std::vector<unsigned> MBB2IdxMap;
-
- typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
- Mi2IndexMap mi2iMap_;
+ SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
- typedef std::vector<MachineInstr*> Index2MiMap;
- Index2MiMap i2miMap_;
+ /// RegUnitIntervals - Keep a live interval for each register unit as a way
+ /// of tracking fixed physreg interference.
+ SmallVector<LiveInterval*, 0> RegUnitIntervals;
- typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
- Reg2IntervalMap r2iMap_;
+ public:
+ static char ID; // Pass identification, replacement for typeid
+ LiveIntervals();
+ virtual ~LiveIntervals();
- typedef IndexedMap<unsigned> Reg2RegMap;
- Reg2RegMap r2rMap_;
+ // Calculate the spill weight to assign to a single instruction.
+ static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
- BitVector allocatableRegs_;
- DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
+ LiveInterval &getInterval(unsigned Reg) {
+ LiveInterval *LI = VirtRegIntervals[Reg];
+ assert(LI && "Interval does not exist for virtual register");
+ return *LI;
+ }
- /// JoinedLIs - Keep track which register intervals have been coalesced
- /// with other intervals.
- BitVector JoinedLIs;
+ const LiveInterval &getInterval(unsigned Reg) const {
+ return const_cast<LiveIntervals*>(this)->getInterval(Reg);
+ }
- public:
- static const int ID; // Pass identifcation, replacement for typeid
- LiveIntervals() : MachineFunctionPass((intptr_t)&ID) {}
-
- struct CopyRec {
- MachineInstr *MI;
- unsigned SrcReg, DstReg;
- };
- CopyRec getCopyRec(MachineInstr *MI, unsigned SrcReg, unsigned DstReg) {
- CopyRec R;
- R.MI = MI;
- R.SrcReg = SrcReg;
- R.DstReg = DstReg;
- return R;
+ bool hasInterval(unsigned Reg) const {
+ return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
+ }
+
+ // Interval creation.
+ LiveInterval &getOrCreateInterval(unsigned Reg) {
+ if (!hasInterval(Reg)) {
+ VirtRegIntervals.grow(Reg);
+ VirtRegIntervals[Reg] = createInterval(Reg);
+ }
+ return getInterval(Reg);
+ }
+
+ // Interval removal.
+ void removeInterval(unsigned Reg) {
+ delete VirtRegIntervals[Reg];
+ VirtRegIntervals[Reg] = 0;
}
- struct InstrSlots {
- enum {
- LOAD = 0,
- USE = 1,
- DEF = 2,
- STORE = 3,
- NUM = 4
- };
- };
-
- static unsigned getBaseIndex(unsigned index) {
- return index - (index % InstrSlots::NUM);
+
+ /// addLiveRangeToEndOfBlock - Given a register and an instruction,
+ /// adds a live range from that instruction to the end of its MBB.
+ LiveRange addLiveRangeToEndOfBlock(unsigned reg,
+ MachineInstr* startInst);
+
+ /// shrinkToUses - After removing some uses of a register, shrink its live
+ /// range to just the remaining uses. This method does not compute reaching
+ /// defs for new uses, and it doesn't remove dead defs.
+ /// Dead PHIDef values are marked as unused.
+ /// New dead machine instructions are added to the dead vector.
+ /// Return true if the interval may have been separated into multiple
+ /// connected components.
+ bool shrinkToUses(LiveInterval *li,
+ SmallVectorImpl<MachineInstr*> *dead = 0);
+
+ /// extendToIndices - Extend the live range of LI to reach all points in
+ /// Indices. The points in the Indices array must be jointly dominated by
+ /// existing defs in LI. PHI-defs are added as needed to maintain SSA form.
+ ///
+ /// If a SlotIndex in Indices is the end index of a basic block, LI will be
+ /// extended to be live out of the basic block.
+ ///
+ /// See also LiveRangeCalc::extend().
+ void extendToIndices(LiveInterval *LI, ArrayRef<SlotIndex> Indices);
+
+ /// pruneValue - If an LI value is live at Kill, prune its live range by
+ /// removing any liveness reachable from Kill. Add live range end points to
+ /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
+ /// value's live range.
+ ///
+ /// Calling pruneValue() and extendToIndices() can be used to reconstruct
+ /// SSA form after adding defs to a virtual register.
+ void pruneValue(LiveInterval *LI, SlotIndex Kill,
+ SmallVectorImpl<SlotIndex> *EndPoints);
+
+ SlotIndexes *getSlotIndexes() const {
+ return Indexes;
+ }
+
+ AliasAnalysis *getAliasAnalysis() const {
+ return AA;
}
- static unsigned getBoundaryIndex(unsigned index) {
- return getBaseIndex(index + InstrSlots::NUM - 1);
+
+ /// isNotInMIMap - returns true if the specified machine instr has been
+ /// removed or was never entered in the map.
+ bool isNotInMIMap(const MachineInstr* Instr) const {
+ return !Indexes->hasIndex(Instr);
}
- static unsigned getLoadIndex(unsigned index) {
- return getBaseIndex(index) + InstrSlots::LOAD;
+
+ /// Returns the base index of the given instruction.
+ SlotIndex getInstructionIndex(const MachineInstr *instr) const {
+ return Indexes->getInstructionIndex(instr);
}
- static unsigned getUseIndex(unsigned index) {
- return getBaseIndex(index) + InstrSlots::USE;
+
+ /// Returns the instruction associated with the given index.
+ MachineInstr* getInstructionFromIndex(SlotIndex index) const {
+ return Indexes->getInstructionFromIndex(index);
}
- static unsigned getDefIndex(unsigned index) {
- return getBaseIndex(index) + InstrSlots::DEF;
+
+ /// Return the first index in the given basic block.
+ SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
+ return Indexes->getMBBStartIdx(mbb);
}
- static unsigned getStoreIndex(unsigned index) {
- return getBaseIndex(index) + InstrSlots::STORE;
+
+ /// Return the last index in the given basic block.
+ SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
+ return Indexes->getMBBEndIdx(mbb);
}
- typedef Reg2IntervalMap::iterator iterator;
- typedef Reg2IntervalMap::const_iterator const_iterator;
- const_iterator begin() const { return r2iMap_.begin(); }
- const_iterator end() const { return r2iMap_.end(); }
- iterator begin() { return r2iMap_.begin(); }
- iterator end() { return r2iMap_.end(); }
- unsigned getNumIntervals() const { return r2iMap_.size(); }
-
- LiveInterval &getInterval(unsigned reg) {
- Reg2IntervalMap::iterator I = r2iMap_.find(reg);
- assert(I != r2iMap_.end() && "Interval does not exist for register");
- return I->second;
+ bool isLiveInToMBB(const LiveInterval &li,
+ const MachineBasicBlock *mbb) const {
+ return li.liveAt(getMBBStartIdx(mbb));
}
- const LiveInterval &getInterval(unsigned reg) const {
- Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
- assert(I != r2iMap_.end() && "Interval does not exist for register");
- return I->second;
+ bool isLiveOutOfMBB(const LiveInterval &li,
+ const MachineBasicBlock *mbb) const {
+ return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
}
- bool hasInterval(unsigned reg) const {
- return r2iMap_.count(reg);
+ MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
+ return Indexes->getMBBFromIndex(index);
}
- /// getMBBStartIdx - Return the base index of the first instruction in the
- /// specified MachineBasicBlock.
- unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
- return getMBBStartIdx(MBB->getNumber());
+ SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
+ return Indexes->insertMachineInstrInMaps(MI);
}
-
- unsigned getMBBStartIdx(unsigned MBBNo) const {
- assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
- return MBB2IdxMap[MBBNo];
+
+ void RemoveMachineInstrFromMaps(MachineInstr *MI) {
+ Indexes->removeMachineInstrFromMaps(MI);
}
- /// getInstructionIndex - returns the base index of instr
- unsigned getInstructionIndex(MachineInstr* instr) const {
- Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
- assert(it != mi2iMap_.end() && "Invalid instruction!");
- return it->second;
+ void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
+ Indexes->replaceMachineInstrInMaps(MI, NewMI);
}
- /// getInstructionFromIndex - given an index in any slot of an
- /// instruction return a pointer the instruction
- MachineInstr* getInstructionFromIndex(unsigned index) const {
- index /= InstrSlots::NUM; // convert index to vector index
- assert(index < i2miMap_.size() &&
- "index does not correspond to an instruction");
- return i2miMap_[index];
+ bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
+ SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
+ return Indexes->findLiveInMBBs(Start, End, MBBs);
}
-
- std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
- VirtRegMap& vrm,
- int slot);
- /// CreateNewLiveInterval - Create a new live interval with the given live
- /// ranges. The new live interval will have an infinite spill weight.
- LiveInterval &CreateNewLiveInterval(const LiveInterval *LI,
- const std::vector<LiveRange> &LRs);
+ VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual void releaseMemory();
virtual bool runOnMachineFunction(MachineFunction&);
/// print - Implement the dump method.
- virtual void print(std::ostream &O, const Module* = 0) const;
- void print(std::ostream *O, const Module* M = 0) const {
- if (O) print(*O, M);
+ virtual void print(raw_ostream &O, const Module* = 0) const;
+
+ /// intervalIsInOneMBB - If LI is confined to a single basic block, return
+ /// a pointer to that block. If LI is live in to or out of any block,
+ /// return NULL.
+ MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
+
+ /// Returns true if VNI is killed by any PHI-def values in LI.
+ /// This may conservatively return true to avoid expensive computations.
+ bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
+
+ /// addKillFlags - Add kill flags to any instruction that kills a virtual
+ /// register.
+ void addKillFlags(const VirtRegMap*);
+
+ /// handleMove - call this method to notify LiveIntervals that
+ /// instruction 'mi' has been moved within a basic block. This will update
+ /// the live intervals for all operands of mi. Moves between basic blocks
+ /// are not supported.
+ ///
+ /// \param UpdateFlags Update live intervals for nonallocatable physregs.
+ void handleMove(MachineInstr* MI, bool UpdateFlags = false);
+
+ /// moveIntoBundle - Update intervals for operands of MI so that they
+ /// begin/end on the SlotIndex for BundleStart.
+ ///
+ /// \param UpdateFlags Update live intervals for nonallocatable physregs.
+ ///
+ /// Requires MI and BundleStart to have SlotIndexes, and assumes
+ /// existing liveness is accurate. BundleStart should be the first
+ /// instruction in the Bundle.
+ void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart,
+ bool UpdateFlags = false);
+
+ // Register mask functions.
+ //
+ // Machine instructions may use a register mask operand to indicate that a
+ // large number of registers are clobbered by the instruction. This is
+ // typically used for calls.
+ //
+ // For compile time performance reasons, these clobbers are not recorded in
+ // the live intervals for individual physical registers. Instead,
+ // LiveIntervalAnalysis maintains a sorted list of instructions with
+ // register mask operands.
+
+ /// getRegMaskSlots - Returns a sorted array of slot indices of all
+ /// instructions with register mask operands.
+ ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
+
+ /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
+ /// instructions with register mask operands in the basic block numbered
+ /// MBBNum.
+ ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
+ std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
+ return getRegMaskSlots().slice(P.first, P.second);
}
- private:
- /// isRemoved - returns true if the specified machine instr has been
- /// removed.
- bool isRemoved(MachineInstr* instr) const {
- return !mi2iMap_.count(instr);
+ /// getRegMaskBits() - Returns an array of register mask pointers
+ /// corresponding to getRegMaskSlots().
+ ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
+
+ /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
+ /// to getRegMaskSlotsInBlock(MBBNum).
+ ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
+ std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
+ return getRegMaskBits().slice(P.first, P.second);
}
- /// RemoveMachineInstrFromMaps - This marks the specified machine instr as
- /// deleted.
- void RemoveMachineInstrFromMaps(MachineInstr *MI) {
- // remove index -> MachineInstr and
- // MachineInstr -> index mappings
- Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
- if (mi2i != mi2iMap_.end()) {
- i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
- mi2iMap_.erase(mi2i);
+ /// checkRegMaskInterference - Test if LI is live across any register mask
+ /// instructions, and compute a bit mask of physical registers that are not
+ /// clobbered by any of them.
+ ///
+ /// Returns false if LI doesn't cross any register mask instructions. In
+ /// that case, the bit vector is not filled in.
+ bool checkRegMaskInterference(LiveInterval &LI,
+ BitVector &UsableRegs);
+
+ // Register unit functions.
+ //
+ // Fixed interference occurs when MachineInstrs use physregs directly
+ // instead of virtual registers. This typically happens when passing
+ // arguments to a function call, or when instructions require operands in
+ // fixed registers.
+ //
+ // Each physreg has one or more register units, see MCRegisterInfo. We
+ // track liveness per register unit to handle aliasing registers more
+ // efficiently.
+
+ /// getRegUnit - Return the live range for Unit.
+ /// It will be computed if it doesn't exist.
+ LiveInterval &getRegUnit(unsigned Unit) {
+ LiveInterval *LI = RegUnitIntervals[Unit];
+ if (!LI) {
+ // Compute missing ranges on demand.
+ RegUnitIntervals[Unit] = LI = new LiveInterval(Unit, HUGE_VALF);
+ computeRegUnitInterval(LI);
}
+ return *LI;
+ }
+
+ /// getCachedRegUnit - Return the live range for Unit if it has already
+ /// been computed, or NULL if it hasn't been computed yet.
+ LiveInterval *getCachedRegUnit(unsigned Unit) {
+ return RegUnitIntervals[Unit];
+ }
+
+ const LiveInterval *getCachedRegUnit(unsigned Unit) const {
+ return RegUnitIntervals[Unit];
}
-
+
+ private:
/// computeIntervals - Compute live intervals.
void computeIntervals();
- /// joinIntervals - join compatible live intervals
- void joinIntervals();
-
- /// CopyCoallesceInMBB - Coallsece copies in the specified MBB, putting
- /// copies that cannot yet be coallesced into the "TryAgain" list.
- void CopyCoallesceInMBB(MachineBasicBlock *MBB,
- std::vector<CopyRec> *TryAgain, bool PhysOnly = false);
-
- /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
- /// which are the src/dst of the copy instruction CopyMI. This returns true
- /// if the copy was successfully coallesced away, or if it is never possible
- /// to coallesce these this copy, due to register constraints. It returns
- /// false if it is not currently possible to coallesce this interval, but
- /// it may be possible if other things get coallesced.
- bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg,
- bool PhysOnly = false);
-
- /// JoinIntervals - Attempt to join these two intervals. On failure, this
- /// returns false. Otherwise, if one of the intervals being joined is a
- /// physreg, this method always canonicalizes DestInt to be it. The output
- /// "SrcInt" will not have been modified, so we can use this information
- /// below to update aliases.
- bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS);
-
- /// SimpleJoin - Attempt to join the specified interval into this one. The
- /// caller of this method must guarantee that the RHS only contains a single
- /// value number and that the RHS is not defined by a copy from this
- /// interval. This returns false if the intervals are not joinable, or it
- /// joins them and returns true.
- bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
-
+ /// Compute live intervals for all virtual registers.
+ void computeVirtRegs();
+
+ /// Compute RegMaskSlots and RegMaskBits.
+ void computeRegMasks();
+
/// handleRegisterDef - update intervals for a register def
- /// (calls handlePhysicalRegisterDef and
- /// handleVirtualRegisterDef)
+ /// (calls handleVirtualRegisterDef)
void handleRegisterDef(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator MI, unsigned MIIdx,
- unsigned reg);
+ MachineBasicBlock::iterator MI,
+ SlotIndex MIIdx,
+ MachineOperand& MO, unsigned MOIdx);
+
+ /// isPartialRedef - Return true if the specified def at the specific index
+ /// is partially re-defining the specified live interval. A common case of
+ /// this is a definition of the sub-register.
+ bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
+ LiveInterval &interval);
/// handleVirtualRegisterDef - update intervals for a virtual
/// register def
void handleVirtualRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
- unsigned MIIdx,
+ SlotIndex MIIdx, MachineOperand& MO,
+ unsigned MOIdx,
LiveInterval& interval);
- /// handlePhysicalRegisterDef - update intervals for a physical register
- /// def.
- void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
- MachineBasicBlock::iterator mi,
- unsigned MIIdx,
- LiveInterval &interval,
- unsigned SrcReg);
-
- /// handleLiveInRegister - Create interval for a livein register.
- void handleLiveInRegister(MachineBasicBlock* mbb,
- unsigned MIIdx,
- LiveInterval &interval, bool isAlias = false);
-
- /// Return true if the two specified registers belong to different
- /// register classes. The registers may be either phys or virt regs.
- bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
-
-
- bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
- MachineInstr *CopyMI);
+ static LiveInterval* createInterval(unsigned Reg);
- /// lastRegisterUse - Returns the last use of the specific register between
- /// cycles Start and End. It also returns the use operand by reference. It
- /// returns NULL if there are no uses.
- MachineInstr *lastRegisterUse(unsigned Reg, unsigned Start, unsigned End,
- MachineOperand *&MOU);
-
- /// findDefOperand - Returns the MachineOperand that is a def of the specific
- /// register. It returns NULL if the def is not found.
- MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg);
-
- /// unsetRegisterKill - Unset IsKill property of all uses of the specific
- /// register of the specific instruction.
- void unsetRegisterKill(MachineInstr *MI, unsigned Reg);
-
- /// hasRegisterDef - True if the instruction defines the specific register.
- ///
- bool hasRegisterDef(MachineInstr *MI, unsigned Reg);
+ void printInstrs(raw_ostream &O) const;
+ void dumpInstrs() const;
- static LiveInterval createInterval(unsigned Reg);
+ void computeLiveInRegUnits();
+ void computeRegUnitInterval(LiveInterval*);
+ void computeVirtRegInterval(LiveInterval*);
- void removeInterval(unsigned Reg) {
- r2iMap_.erase(Reg);
- }
-
- LiveInterval &getOrCreateInterval(unsigned reg) {
- Reg2IntervalMap::iterator I = r2iMap_.find(reg);
- if (I == r2iMap_.end())
- I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
- return I->second;
- }
-
- /// rep - returns the representative of this register
- unsigned rep(unsigned Reg) {
- unsigned Rep = r2rMap_[Reg];
- if (Rep)
- return r2rMap_[Reg] = rep(Rep);
- return Reg;
- }
-
- void printRegName(unsigned reg) const;
+ class HMEditor;
};
-
} // End llvm namespace
#endif
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