class LiveVariables : public MachineFunctionPass {
public:
+ /// VarInfo - This represents the regions where a virtual register is live in
+ /// the program. We represent this with three difference pieces of
+ /// information: the instruction that uniquely defines the value, the set of
+ /// blocks the instruction is live into and live out of, and the set of
+ /// non-phi instructions that are the last users of the value.
+ ///
+ /// In the common case where a value is defined and killed in the same block,
+ /// DefInst is the defining inst, there is one killing instruction, and
+ /// AliveBlocks is empty.
+ ///
+ /// Otherwise, the value is live out of the block. If the value is live
+ /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
+ /// the liveness range ends are not included in AliveBlocks, instead being
+ /// captured by the Kills set. In these blocks, the value is live into the
+ /// block (unless the value is defined and killed in the same block) and lives
+ /// until the specified instruction. Note that there cannot ever be a value
+ /// whose Kills set contains two instructions from the same basic block.
+ ///
+ /// PHI nodes complicate things a bit. If a PHI node is the last user of a
+ /// value in one of its predecessor blocks, it is not listed in the kills set,
+ /// but does include the predecessor block in the AliveBlocks set (unless that
+ /// block also defines the value). This leads to the (perfectly sensical)
+ /// situation where a value is defined in a block, and the last use is a phi
+ /// node in the successor. In this case, DefInst will be the defining
+ /// instruction, AliveBlocks is empty (the value is not live across any
+ /// blocks) and Kills is empty (phi nodes are not included). This is sensical
+ /// because the value must be live to the end of the block, but is not live in
+ /// any successor blocks.
struct VarInfo {
/// DefInst - The machine instruction that defines this register.
- MachineInstr *DefInst;
+ ///
+ MachineInstr *DefInst;
/// AliveBlocks - Set of blocks of which this value is alive completely
/// through. This is a bit set which uses the basic block number as an
}
return false;
}
+
+ void dump() const;
};
private:
///
std::vector<VarInfo> VirtRegInfo;
- /// RegistersKilled - This multimap keeps track of all of the registers that
+ /// RegistersKilled - This map keeps track of all of the registers that
/// are dead immediately after an instruction reads its operands. If an
/// instruction does not have an entry in this map, it kills no registers.
///
- std::multimap<MachineInstr*, unsigned> RegistersKilled;
+ std::map<MachineInstr*, std::vector<unsigned> > RegistersKilled;
- /// RegistersDead - This multimap keeps track of all of the registers that are
+ /// RegistersDead - This map keeps track of all of the registers that are
/// dead immediately after an instruction executes, which are not dead after
/// the operands are evaluated. In practice, this only contains registers
/// which are defined by an instruction, but never used.
///
- std::multimap<MachineInstr*, unsigned> RegistersDead;
+ std::map<MachineInstr*, std::vector<unsigned> > RegistersDead;
+
+ /// Dummy - An always empty vector used for instructions without dead or
+ /// killed operands.
+ std::vector<unsigned> Dummy;
/// AllocatablePhysicalRegisters - This vector keeps track of which registers
/// are actually register allocatable by the target machine. We can not track
/// killed_iterator - Iterate over registers killed by a machine instruction
///
- typedef std::multimap<MachineInstr*, unsigned>::iterator killed_iterator;
+ typedef std::vector<unsigned>::iterator killed_iterator;
+ std::vector<unsigned> &getKillsVector(MachineInstr *MI) {
+ std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
+ RegistersKilled.find(MI);
+ return I != RegistersKilled.end() ? I->second : Dummy;
+ }
+ std::vector<unsigned> &getDeadDefsVector(MachineInstr *MI) {
+ std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
+ RegistersDead.find(MI);
+ return I != RegistersDead.end() ? I->second : Dummy;
+ }
+
+
/// killed_begin/end - Get access to the range of registers killed by a
/// machine instruction.
killed_iterator killed_begin(MachineInstr *MI) {
- return RegistersKilled.lower_bound(MI);
+ return getKillsVector(MI).begin();
}
killed_iterator killed_end(MachineInstr *MI) {
- return RegistersKilled.upper_bound(MI);
+ return getKillsVector(MI).end();
}
std::pair<killed_iterator, killed_iterator>
killed_range(MachineInstr *MI) {
- return RegistersKilled.equal_range(MI);
+ std::vector<unsigned> &V = getKillsVector(MI);
+ return std::make_pair(V.begin(), V.end());
}
/// KillsRegister - Return true if the specified instruction kills the
/// specified register.
- bool KillsRegister(MachineInstr *MI, unsigned Reg) {
- std::pair<killed_iterator, killed_iterator> KIP = killed_range(MI);
- for (; KIP.first != KIP.second; ++KIP.first)
- if (KIP.first->second == Reg)
- return true;
- return false;
- }
-
+ bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
+
killed_iterator dead_begin(MachineInstr *MI) {
- return RegistersDead.lower_bound(MI);
+ return getDeadDefsVector(MI).begin();
}
killed_iterator dead_end(MachineInstr *MI) {
- return RegistersDead.upper_bound(MI);
+ return getDeadDefsVector(MI).end();
}
std::pair<killed_iterator, killed_iterator>
dead_range(MachineInstr *MI) {
- return RegistersDead.equal_range(MI);
+ std::vector<unsigned> &V = getDeadDefsVector(MI);
+ return std::make_pair(V.begin(), V.end());
}
-
+
+ /// RegisterDefIsDead - Return true if the specified instruction defines the
+ /// specified register, but that definition is dead.
+ bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
+
//===--------------------------------------------------------------------===//
// API to update live variable information
/// instruction.
///
void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
- RegistersKilled.insert(std::make_pair(MI, IncomingReg));
+ std::vector<unsigned> &V = RegistersKilled[MI];
+ // Insert in a sorted order.
+ if (V.empty() || IncomingReg > V.back()) {
+ V.push_back(IncomingReg);
+ } else {
+ std::vector<unsigned>::iterator I = V.begin();
+ for (; *I < IncomingReg; ++I)
+ /*empty*/;
+ if (*I != IncomingReg) // Don't insert duplicates.
+ V.insert(I, IncomingReg);
+ }
getVarInfo(IncomingReg).Kills.push_back(MI);
}
MachineInstr *MI) {
if (!getVarInfo(reg).removeKill(MI))
return false;
- for (killed_iterator i = killed_begin(MI), e = killed_end(MI); i != e; ) {
- if (i->second == reg)
- RegistersKilled.erase(i++);
- else
- ++i;
- }
+
+ std::vector<unsigned> &V = getKillsVector(MI);
+ for (unsigned i = 0, e = V.size(); i != e; ++i)
+ if (V[i] == reg) {
+ V.erase(V.begin()+i);
+ return true;
+ }
return true;
}
- /// removeVirtualRegistersKilled - Remove all of the specified killed
- /// registers from the live variable information.
- void removeVirtualRegistersKilled(killed_iterator B, killed_iterator E) {
- for (killed_iterator I = B; I != E; ++I) { // Remove VarInfo entries...
- bool removed = getVarInfo(I->second).removeKill(I->first);
- assert(removed && "kill not in register's VarInfo?");
+ /// removeVirtualRegistersKilled - Remove all killed info for the specified
+ /// instruction.
+ void removeVirtualRegistersKilled(MachineInstr *MI) {
+ std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
+ RegistersKilled.find(MI);
+ if (I != RegistersKilled.end()) {
+ std::vector<unsigned> &Regs = I->second;
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ bool removed = getVarInfo(Regs[i]).removeKill(MI);
+ assert(removed && "kill not in register's VarInfo?");
+ }
+ RegistersKilled.erase(I);
}
- RegistersKilled.erase(B, E);
}
/// addVirtualRegisterDead - Add information about the fact that the specified
/// register is dead after being used by the specified instruction.
///
void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
- RegistersDead.insert(std::make_pair(MI, IncomingReg));
+ std::vector<unsigned> &V = RegistersDead[MI];
+ // Insert in a sorted order.
+ if (V.empty() || IncomingReg > V.back()) {
+ V.push_back(IncomingReg);
+ } else {
+ std::vector<unsigned>::iterator I = V.begin();
+ for (; *I < IncomingReg; ++I)
+ /*empty*/;
+ if (*I != IncomingReg) // Don't insert duplicates.
+ V.insert(I, IncomingReg);
+ }
getVarInfo(IncomingReg).Kills.push_back(MI);
}
if (!getVarInfo(reg).removeKill(MI))
return false;
- for (killed_iterator i = killed_begin(MI), e = killed_end(MI); i != e; ) {
- if (i->second == reg)
- RegistersKilled.erase(i++);
- else
- ++i;
- }
+ std::vector<unsigned> &V = getDeadDefsVector(MI);
+ for (unsigned i = 0, e = V.size(); i != e; ++i)
+ if (V[i] == reg) {
+ V.erase(V.begin()+i);
+ return true;
+ }
return true;
}
/// removeVirtualRegistersDead - Remove all of the specified dead
/// registers from the live variable information.
- void removeVirtualRegistersDead(killed_iterator B, killed_iterator E) {
- for (killed_iterator I = B; I != E; ++I) // Remove VarInfo entries...
- getVarInfo(I->second).removeKill(I->first);
- RegistersDead.erase(B, E);
+ void removeVirtualRegistersDead(MachineInstr *MI) {
+ std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
+ RegistersDead.find(MI);
+ if (I != RegistersDead.end()) {
+ std::vector<unsigned> &Regs = I->second;
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ bool removed = getVarInfo(Regs[i]).removeKill(MI);
+ assert(removed && "kill not in register's VarInfo?");
+ }
+ RegistersDead.erase(I);
+ }
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *BB);
void HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
- MachineInstr *MI);
+ MachineInstr *MI);
};
} // End llvm namespace
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