class LiveVariables : public MachineFunctionPass {
public:
+ /// VarInfo - This represents the regions where a virtual register is live in
+ /// the program. We represent this with three difference pieces of
+ /// information: the instruction that uniquely defines the value, the set of
+ /// blocks the instruction is live into and live out of, and the set of
+ /// non-phi instructions that are the last users of the value.
+ ///
+ /// In the common case where a value is defined and killed in the same block,
+ /// DefInst is the defining inst, there is one killing instruction, and
+ /// AliveBlocks is empty.
+ ///
+ /// Otherwise, the value is live out of the block. If the value is live
+ /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
+ /// the liveness range ends are not included in AliveBlocks, instead being
+ /// captured by the Kills set. In these blocks, the value is live into the
+ /// block (unless the value is defined and killed in the same block) and lives
+ /// until the specified instruction. Note that there cannot ever be a value
+ /// whose Kills set contains two instructions from the same basic block.
+ ///
+ /// PHI nodes complicate things a bit. If a PHI node is the last user of a
+ /// value in one of its predecessor blocks, it is not listed in the kills set,
+ /// but does include the predecessor block in the AliveBlocks set (unless that
+ /// block also defines the value). This leads to the (perfectly sensical)
+ /// situation where a value is defined in a block, and the last use is a phi
+ /// node in the successor. In this case, DefInst will be the defining
+ /// instruction, AliveBlocks is empty (the value is not live across any
+ /// blocks) and Kills is empty (phi nodes are not included). This is sensical
+ /// because the value must be live to the end of the block, but is not live in
+ /// any successor blocks.
struct VarInfo {
/// DefInst - The machine instruction that defines this register.
///
}
return false;
}
+
+ void dump() const;
};
private:
/// KillsRegister - Return true if the specified instruction kills the
/// specified register.
- bool KillsRegister(MachineInstr *MI, unsigned Reg) const {
- std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
- RegistersKilled.find(MI);
- if (I != RegistersKilled.end())
- for (std::vector<unsigned>::const_iterator CI = I->second.begin(),
- E = I->second.end(); CI != E; ++CI)
- if (*CI == Reg) return true;
- return false;
- }
-
+ bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
+
killed_iterator dead_begin(MachineInstr *MI) {
return getDeadDefsVector(MI).begin();
}
/// RegisterDefIsDead - Return true if the specified instruction defines the
/// specified register, but that definition is dead.
- bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
- std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
- RegistersDead.find(MI);
- if (I != RegistersDead.end())
- for (std::vector<unsigned>::const_iterator CI = I->second.begin(),
- E = I->second.end(); CI != E; ++CI)
- if (*CI == Reg) return true;
- return false;
- }
-
+ bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
+
//===--------------------------------------------------------------------===//
// API to update live variable information
/// instruction.
///
void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
- RegistersKilled.insert(std::make_pair(MI, IncomingReg));
+ std::vector<unsigned> &V = RegistersKilled[MI];
+ // Insert in a sorted order.
+ if (V.empty() || IncomingReg > V.back()) {
+ V.push_back(IncomingReg);
+ } else {
+ std::vector<unsigned>::iterator I = V.begin();
+ for (; *I < IncomingReg; ++I)
+ /*empty*/;
+ if (*I != IncomingReg) // Don't insert duplicates.
+ V.insert(I, IncomingReg);
+ }
getVarInfo(IncomingReg).Kills.push_back(MI);
}
/// removeVirtualRegistersKilled - Remove all killed info for the specified
/// instruction.
void removeVirtualRegistersKilled(MachineInstr *MI) {
- RegistersKilled.erase(MI);
+ std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
+ RegistersKilled.find(MI);
+ if (I != RegistersKilled.end()) {
+ std::vector<unsigned> &Regs = I->second;
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ bool removed = getVarInfo(Regs[i]).removeKill(MI);
+ assert(removed && "kill not in register's VarInfo?");
+ }
+ RegistersKilled.erase(I);
+ }
}
/// addVirtualRegisterDead - Add information about the fact that the specified
/// register is dead after being used by the specified instruction.
///
void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
- RegistersDead.insert(std::make_pair(MI, IncomingReg));
+ std::vector<unsigned> &V = RegistersDead[MI];
+ // Insert in a sorted order.
+ if (V.empty() || IncomingReg > V.back()) {
+ V.push_back(IncomingReg);
+ } else {
+ std::vector<unsigned>::iterator I = V.begin();
+ for (; *I < IncomingReg; ++I)
+ /*empty*/;
+ if (*I != IncomingReg) // Don't insert duplicates.
+ V.insert(I, IncomingReg);
+ }
getVarInfo(IncomingReg).Kills.push_back(MI);
}
/// removeVirtualRegistersDead - Remove all of the specified dead
/// registers from the live variable information.
void removeVirtualRegistersDead(MachineInstr *MI) {
- RegistersDead.erase(MI);
+ std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
+ RegistersDead.find(MI);
+ if (I != RegistersDead.end()) {
+ std::vector<unsigned> &Regs = I->second;
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ bool removed = getVarInfo(Regs[i]).removeKill(MI);
+ assert(removed && "kill not in register's VarInfo?");
+ }
+ RegistersDead.erase(I);
+ }
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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