#define LLVM_CODEGEN_LIVEVARIABLES_H
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/ADT/BitVector.h"
#include <map>
namespace llvm {
class MRegisterInfo;
+class BitVector;
class LiveVariables : public MachineFunctionPass {
public:
+ /// VarInfo - This represents the regions where a virtual register is live in
+ /// the program. We represent this with three different pieces of
+ /// information: the instruction that uniquely defines the value, the set of
+ /// blocks the instruction is live into and live out of, and the set of
+ /// non-phi instructions that are the last users of the value.
+ ///
+ /// In the common case where a value is defined and killed in the same block,
+ /// DefInst is the defining inst, there is one killing instruction, and
+ /// AliveBlocks is empty.
+ ///
+ /// Otherwise, the value is live out of the block. If the value is live
+ /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
+ /// the liveness range ends are not included in AliveBlocks, instead being
+ /// captured by the Kills set. In these blocks, the value is live into the
+ /// block (unless the value is defined and killed in the same block) and lives
+ /// until the specified instruction. Note that there cannot ever be a value
+ /// whose Kills set contains two instructions from the same basic block.
+ ///
+ /// PHI nodes complicate things a bit. If a PHI node is the last user of a
+ /// value in one of its predecessor blocks, it is not listed in the kills set,
+ /// but does include the predecessor block in the AliveBlocks set (unless that
+ /// block also defines the value). This leads to the (perfectly sensical)
+ /// situation where a value is defined in a block, and the last use is a phi
+ /// node in the successor. In this case, DefInst will be the defining
+ /// instruction, AliveBlocks is empty (the value is not live across any
+ /// blocks) and Kills is empty (phi nodes are not included). This is sensical
+ /// because the value must be live to the end of the block, but is not live in
+ /// any successor blocks.
struct VarInfo {
/// DefInst - The machine instruction that defines this register.
///
/// through. This is a bit set which uses the basic block number as an
/// index.
///
- std::vector<bool> AliveBlocks;
+ BitVector AliveBlocks;
+
+ /// UsedBlocks - Set of blocks of which this value is actually used. This
+ /// is a bit set which uses the basic block number as an index.
+ BitVector UsedBlocks;
/// Kills - List of MachineInstruction's which are the last use of this
/// virtual register (kill it) in their basic block.
}
return false;
}
+
+ void dump() const;
};
private:
///
std::vector<VarInfo> VirtRegInfo;
- /// RegistersKilled - This map keeps track of all of the registers that
- /// are dead immediately after an instruction reads its operands. If an
- /// instruction does not have an entry in this map, it kills no registers.
- ///
- std::map<MachineInstr*, std::vector<unsigned> > RegistersKilled;
-
- /// RegistersDead - This map keeps track of all of the registers that are
- /// dead immediately after an instruction executes, which are not dead after
- /// the operands are evaluated. In practice, this only contains registers
- /// which are defined by an instruction, but never used.
- ///
- std::map<MachineInstr*, std::vector<unsigned> > RegistersDead;
-
- /// Dummy - An always empty vector used for instructions without dead or
- /// killed operands.
- std::vector<unsigned> Dummy;
-
- /// AllocatablePhysicalRegisters - This vector keeps track of which registers
- /// are actually register allocatable by the target machine. We can not track
- /// liveness for values that are not in this set.
+ /// ReservedRegisters - This vector keeps track of which registers
+ /// are reserved register which are not allocatable by the target machine.
+ /// We can not track liveness for values that are in this set.
///
- std::vector<bool> AllocatablePhysicalRegisters;
+ BitVector ReservedRegisters;
private: // Intermediate data structures
+ MachineFunction *MF;
+
const MRegisterInfo *RegInfo;
MachineInstr **PhysRegInfo;
bool *PhysRegUsed;
+ typedef std::map<const MachineBasicBlock*,
+ std::vector<unsigned> > PHIVarInfoMap;
+
+ PHIVarInfoMap PHIVarInfo;
+
+
+ /// addRegisterKilled - We have determined MI kills a register. Look for the
+ /// operand that uses it and mark it as IsKill.
+ void addRegisterKilled(unsigned IncomingReg, MachineInstr *MI);
+
+ /// addRegisterDead - We have determined MI defined a register without a use.
+ /// Look for the operand that defines it and mark it as IsDead.
+ void addRegisterDead(unsigned IncomingReg, MachineInstr *MI);
+
void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
+ /// analyzePHINodes - Gather information about the PHI nodes in here. In
+ /// particular, we want to map the variable information of a virtual
+ /// register which is used in a PHI node. We map that to the BB the vreg
+ /// is coming from.
+ void analyzePHINodes(const MachineFunction& Fn);
public:
virtual bool runOnMachineFunction(MachineFunction &MF);
- /// killed_iterator - Iterate over registers killed by a machine instruction
- ///
- typedef std::vector<unsigned>::iterator killed_iterator;
-
- std::vector<unsigned> &getKillsVector(MachineInstr *MI) {
- std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
- RegistersKilled.find(MI);
- return I != RegistersKilled.end() ? I->second : Dummy;
- }
- std::vector<unsigned> &getDeadDefsVector(MachineInstr *MI) {
- std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
- RegistersDead.find(MI);
- return I != RegistersDead.end() ? I->second : Dummy;
- }
-
-
- /// killed_begin/end - Get access to the range of registers killed by a
- /// machine instruction.
- killed_iterator killed_begin(MachineInstr *MI) {
- return getKillsVector(MI).begin();
- }
- killed_iterator killed_end(MachineInstr *MI) {
- return getKillsVector(MI).end();
- }
- std::pair<killed_iterator, killed_iterator>
- killed_range(MachineInstr *MI) {
- std::vector<unsigned> &V = getKillsVector(MI);
- return std::make_pair(V.begin(), V.end());
- }
-
/// KillsRegister - Return true if the specified instruction kills the
/// specified register.
- bool KillsRegister(MachineInstr *MI, unsigned Reg) const {
- std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
- RegistersKilled.find(MI);
- if (I != RegistersKilled.end())
- for (std::vector<unsigned>::const_iterator CI = I->second.begin(),
- E = I->second.end(); CI != E; ++CI)
- if (*CI == Reg) return true;
- return false;
- }
-
- killed_iterator dead_begin(MachineInstr *MI) {
- return getDeadDefsVector(MI).begin();
- }
- killed_iterator dead_end(MachineInstr *MI) {
- return getDeadDefsVector(MI).end();
- }
- std::pair<killed_iterator, killed_iterator>
- dead_range(MachineInstr *MI) {
- std::vector<unsigned> &V = getDeadDefsVector(MI);
- return std::make_pair(V.begin(), V.end());
- }
+ bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
/// RegisterDefIsDead - Return true if the specified instruction defines the
/// specified register, but that definition is dead.
- bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
- std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
- RegistersDead.find(MI);
- if (I != RegistersDead.end())
- for (std::vector<unsigned>::const_iterator CI = I->second.begin(),
- E = I->second.end(); CI != E; ++CI)
- if (*CI == Reg) return true;
- return false;
- }
+ bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
+ /// ModifiesRegister - Return true if the specified instruction modifies the
+ /// specified register.
+ bool ModifiesRegister(MachineInstr *MI, unsigned Reg) const;
+
//===--------------------------------------------------------------------===//
// API to update live variable information
/// instruction.
///
void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
- RegistersKilled.insert(std::make_pair(MI, IncomingReg));
- getVarInfo(IncomingReg).Kills.push_back(MI);
- }
+ addRegisterKilled(IncomingReg, MI);
+ getVarInfo(IncomingReg).Kills.push_back(MI);
+ }
/// removeVirtualRegisterKilled - Remove the specified virtual
/// register from the live variable information. Returns true if the
if (!getVarInfo(reg).removeKill(MI))
return false;
- std::vector<unsigned> &V = getKillsVector(MI);
- for (unsigned i = 0, e = V.size(); i != e; ++i)
- if (V[i] == reg) {
- V.erase(V.begin()+i);
- return true;
+ bool Removed = false;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isUse() && MO.getReg() == reg) {
+ MO.unsetIsKill();
+ Removed = true;
+ break;
}
+ }
+
+ assert(Removed && "Register is not used by this instruction!");
return true;
}
/// removeVirtualRegistersKilled - Remove all killed info for the specified
/// instruction.
- void removeVirtualRegistersKilled(MachineInstr *MI) {
- RegistersKilled.erase(MI);
- }
-
+ void removeVirtualRegistersKilled(MachineInstr *MI);
+
/// addVirtualRegisterDead - Add information about the fact that the specified
/// register is dead after being used by the specified instruction.
///
void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
- RegistersDead.insert(std::make_pair(MI, IncomingReg));
+ addRegisterDead(IncomingReg, MI);
getVarInfo(IncomingReg).Kills.push_back(MI);
}
if (!getVarInfo(reg).removeKill(MI))
return false;
- std::vector<unsigned> &V = getDeadDefsVector(MI);
- for (unsigned i = 0, e = V.size(); i != e; ++i)
- if (V[i] == reg) {
- V.erase(V.begin()+i);
- return true;
+ bool Removed = false;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
+ MO.unsetIsDead();
+ Removed = true;
+ break;
}
+ }
+ assert(Removed && "Register is not defined by this instruction!");
return true;
}
- /// removeVirtualRegistersDead - Remove all of the specified dead
- /// registers from the live variable information.
- void removeVirtualRegistersDead(MachineInstr *MI) {
- RegistersDead.erase(MI);
- }
-
+ /// removeVirtualRegistersDead - Remove all of the dead registers for the
+ /// specified instruction from the live variable information.
+ void removeVirtualRegistersDead(MachineInstr *MI);
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
}
virtual void releaseMemory() {
VirtRegInfo.clear();
- RegistersKilled.clear();
- RegistersDead.clear();
}
/// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
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