#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H
-#include "llvm/ADT/alist.h"
+#include "llvm/ADT/ilist.h"
+#include "llvm/ADT/ilist_node.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/Target/TargetInstrDesc.h"
+#include "llvm/CodeGen/DebugLoc.h"
+#include <list>
#include <vector>
namespace llvm {
//===----------------------------------------------------------------------===//
/// MachineInstr - Representation of each machine instruction.
///
-class MachineInstr {
+class MachineInstr : public ilist_node<MachineInstr> {
const TargetInstrDesc *TID; // Instruction descriptor.
unsigned short NumImplicitOps; // Number of implicit operands (which
// are determined at construction time).
std::vector<MachineOperand> Operands; // the operands
- alist<MachineMemOperand> MemOperands; // information on memory references
+ std::list<MachineMemOperand> MemOperands; // information on memory references
MachineBasicBlock *Parent; // Pointer to the owning basic block.
+ DebugLoc debugLoc; // Source line information.
// OperandComplete - Return true if it's illegal to add a new operand
bool OperandsComplete() const;
void operator=(const MachineInstr&); // DO NOT IMPLEMENT
// Intrusive list support
- friend struct alist_traits<MachineInstr>;
- friend struct alist_traits<MachineBasicBlock>;
+ friend struct ilist_traits<MachineInstr>;
+ friend struct ilist_traits<MachineBasicBlock>;
+ friend struct ilist_sentinel_traits<MachineInstr>;
void setParent(MachineBasicBlock *P) { Parent = P; }
/// MachineInstr ctor - This constructor creates a copy of the given
/// TID NULL and no operands.
MachineInstr();
+ // The next two constructors have DebugLoc and non-DebugLoc versions;
+ // over time, the non-DebugLoc versions should be phased out and eventually
+ // removed.
+
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for number of operands specified by
- /// TargetInstrDesc.
+ /// TargetInstrDesc. The version with a DebugLoc should be preferred.
explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic
- /// block.
+ /// block. The version with a DebugLoc should be preferred.
///
MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
+ /// MachineInstr ctor - This constructor create a MachineInstr and add the
+ /// implicit operands. It reserves space for number of operands specified by
+ /// TargetInstrDesc. An explicit DebugLoc is supplied.
+ explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
+ bool NoImp = false);
+
+ /// MachineInstr ctor - Work exactly the same as the ctor above, except that
+ /// the MachineInstr is created and added to the end of the specified basic
+ /// block.
+ ///
+ MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
+ const TargetInstrDesc &TID);
+
~MachineInstr();
// MachineInstrs are pool-allocated and owned by MachineFunction.
public:
const MachineBasicBlock* getParent() const { return Parent; }
MachineBasicBlock* getParent() { return Parent; }
+
+ /// getDebugLoc - Returns the debug location id of this MachineInstr.
+ ///
+ const DebugLoc getDebugLoc() const { return debugLoc; }
/// getDesc - Returns the target instruction descriptor of this
/// MachineInstr.
/// getOpcode - Returns the opcode of this MachineInstr.
///
- int getOpcode() const;
+ int getOpcode() const { return TID->Opcode; }
/// Access to explicit operands of the instruction.
///
unsigned getNumExplicitOperands() const;
/// Access to memory operands of the instruction
- alist<MachineMemOperand>::iterator memoperands_begin()
+ std::list<MachineMemOperand>::iterator memoperands_begin()
{ return MemOperands.begin(); }
- alist<MachineMemOperand>::iterator memoperands_end()
+ std::list<MachineMemOperand>::iterator memoperands_end()
{ return MemOperands.end(); }
- alist<MachineMemOperand>::const_iterator memoperands_begin() const
+ std::list<MachineMemOperand>::const_iterator memoperands_begin() const
{ return MemOperands.begin(); }
- alist<MachineMemOperand>::const_iterator memoperands_end() const
+ std::list<MachineMemOperand>::const_iterator memoperands_end() const
{ return MemOperands.end(); }
bool memoperands_empty() const { return MemOperands.empty(); }
/// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
/// a pointer to the MachineOperand rather than an index.
- MachineOperand *findRegisterDefOperand(unsigned Reg,bool isDead = false,
+ MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
const TargetRegisterInfo *TRI = NULL) {
int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
return (Idx == -1) ? NULL : &getOperand(Idx);
/// none is found.
int findFirstPredOperandIdx() const;
- /// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
+ /// isRegReDefinedByTwoAddr - Given the index of a register def operand,
/// check if the register def is a re-definition due to two addr elimination.
- bool isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const;
+ bool isRegReDefinedByTwoAddr(unsigned DefIdx) const;
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
///
/// isSafeToMove - Return true if it is safe to move this instruction. If
/// SawStore is set to true, it means that there is a store (or call) between
/// the instruction's location and its intended destination.
- bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore);
+ bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) const;
+
+ /// isSafeToReMat - Return true if it's safe to rematerialize the specified
+ /// instruction which defined the specified register instead of copying it.
+ bool isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) const;
+
+ /// hasVolatileMemoryRef - Return true if this instruction may have a
+ /// volatile memory reference, or if the information describing the
+ /// memory reference is not available. Return false if it is known to
+ /// have no volatile memory references.
+ bool hasVolatileMemoryRef() const;
//
// Debugging support
}
void print(std::ostream &OS, const TargetMachine *TM = 0) const;
void print(std::ostream *OS) const { if (OS) print(*OS); }
+ void print(raw_ostream *OS, const TargetMachine *TM) const {
+ if (OS) print(*OS, TM);
+ }
+ void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
+ void print(raw_ostream *OS) const { if (OS) print(*OS); }
void dump() const;
//===--------------------------------------------------------------------===//
///
void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
+ /// setDebugLoc - Replace current source information with new such.
+ /// Avoid using this, the constructor argument is preferable.
+ ///
+ void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
+
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
///
return OS;
}
+inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
+ MI.print(OS);
+ return OS;
+}
+
} // End llvm namespace
#endif