Register scavenger is now capable of scavenging. It spills a register whose use of...

[oota-llvm.git] / include / llvm / CodeGen / MachineInstr.h

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 11a769c930c98656e2c662860f5c89c5839fe891..3351aa802103dc20df72f78377fadcf85d4d6605 100644 (file)
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -76,6 +76,10 @@ private:
   int offset;
 
   MachineOperand() {}
+
+  void print(std::ostream &os) const;
+  void print(std::ostream *os) const { if (os) print(*os); }
+
 public:
   MachineOperand(const MachineOperand &M) {
     *this = M;
@@ -276,20 +280,20 @@ public:
   /// ChangeToRegister - Replace this operand with a new register operand of
   /// the specified value.  If an operand is known to be an register already,
   /// the setReg method should be used.
-  void ChangeToRegister(unsigned Reg, bool isDef) {
+  void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
+                        bool isKill = false, bool isDead = false) {
     opType = MO_Register;
     contents.RegNo = Reg;
     IsDef = isDef;
-    IsImp = false;
-    IsKill = false;
-    IsDead = false;
+    IsImp = isImp;
+    IsKill = isKill;
+    IsDead = isDead;
   }
 
-  friend llvm_ostream& operator<<(llvm_ostream& os, const MachineOperand& mop) {
-    if (os.stream()) *os.stream() << mop;
+  friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {
+    mop.print(os);
     return os;
   }
-  friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
 
   friend class MachineInstr;
 };
@@ -299,7 +303,7 @@ public:
 /// MachineInstr - Representation of each machine instruction.
 ///
 class MachineInstr {
-  short Opcode;                         // the opcode
+  const TargetInstrDescriptor *TID;     // Instruction descriptor.
   unsigned short NumImplicitOps;        // Number of implicit operands (which
                                         // are determined at construction time).
 
@@ -319,7 +323,7 @@ class MachineInstr {
 
 public:
   /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
-  /// opcode 0 and no operands.
+  /// TID NULL and no operands.
   MachineInstr();
 
   /// MachineInstr ctor - This constructor create a MachineInstr and add the
@@ -337,10 +341,14 @@ public:
 
   const MachineBasicBlock* getParent() const { return parent; }
   MachineBasicBlock* getParent() { return parent; }
+  
+  /// getInstrDescriptor - Returns the target instruction descriptor of this
+  /// MachineInstr.
+  const TargetInstrDescriptor *getInstrDescriptor() const { return TID; }
 
   /// getOpcode - Returns the opcode of this MachineInstr.
   ///
-  const int getOpcode() const { return Opcode; }
+  const int getOpcode() const;
 
   /// Access to explicit operands of the instruction.
   ///
@@ -382,39 +390,33 @@ public:
     delete removeFromParent();
   }
 
+  /// findRegisterUseOperand() - Returns the MachineOperand that is a use of
+  /// the specific register or NULL if it is not found. It further tightening
+  /// the search criteria to a use that kills the register if isKill is true.
+  MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false);
+  
+  /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
+  /// the specific register or NULL if it is not found.
+  MachineOperand *findRegisterDefOperand(unsigned Reg);
+  
   /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
   ///
-  void copyKillDeadInfo(const MachineInstr *MI) {
-    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      const MachineOperand &MO = MI->getOperand(i);
-      if (MO.isReg() && (MO.isKill() || MO.isDead())) {
-        for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
-          MachineOperand &MOp = getOperand(j);
-          if (MOp.isIdenticalTo(MO)) {
-            if (MO.isKill())
-              MOp.setIsKill();
-            else
-              MOp.setIsDead();
-            break;
-          }
-        }
-      }
-    }
-  }
+  void copyKillDeadInfo(const MachineInstr *MI);
 
   //
   // Debugging support
   //
-  void print(llvm_ostream &OS, const TargetMachine *TM) const {
-    if (OS.stream()) print(*OS.stream(), TM);
+  void print(std::ostream *OS, const TargetMachine *TM) const {
+    if (OS) print(*OS, TM);
   }
   void print(std::ostream &OS, const TargetMachine *TM) const;
+  void print(std::ostream &OS) const;
+  void print(std::ostream *OS) const { if (OS) print(*OS); }
   void dump() const;
-  friend llvm_ostream& operator<<(llvm_ostream& os, const MachineInstr& minstr){
-    if (os.stream()) *os.stream() << minstr;
+  friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr){
+    minstr.print(os);
     return os;
   }
-  friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
 
   //===--------------------------------------------------------------------===//
   // Accessors to add operands when building up machine instructions.
@@ -500,9 +502,10 @@ public:
   // Accessors used to modify instructions in place.
   //
 
-  /// setOpcode - Replace the opcode of the current instruction with a new one.
+  /// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
+  /// the current instruction with a new one.
   ///
-  void setOpcode(unsigned Op) { Opcode = Op; }
+  void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
 
   /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
   /// fewer operand than it started with.
@@ -525,7 +528,7 @@ private:
 
   /// addImplicitDefUseOperands - Add all implicit def and use operands to
   /// this instruction.
-  void addImplicitDefUseOperands(const TargetInstrDescriptor &TID);
+  void addImplicitDefUseOperands();
 };
 
 //===----------------------------------------------------------------------===//