#include "llvm/ADT/iterator"
#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/Streams.h"
#include <vector>
#include <cassert>
+#include <iosfwd>
namespace llvm {
class Value;
class Function;
class MachineBasicBlock;
+class TargetInstrDescriptor;
class TargetMachine;
class GlobalValue;
MachineOperandType opType:8; // Discriminate the union.
bool IsDef : 1; // True if this is a def, false if this is a use.
+ bool IsImp : 1; // True if this is an implicit def or use.
+
+ bool IsKill : 1; // True if this is a reg use and the reg is dead
+ // immediately after the read.
+ bool IsDead : 1; // True if this is a reg def and the reg is dead
+ // immediately after the write. i.e. A register
+ // that is defined but never used.
/// offset - Offset to address of global or external, only valid for
/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
int offset;
MachineOperand() {}
+
+ void print(std::ostream &os) const;
+ void print(std::ostream *os) const { if (os) print(*os); }
+
public:
MachineOperand(const MachineOperand &M) {
*this = M;
Op.opType = MachineOperand::MO_Immediate;
Op.contents.immedVal = Val;
Op.IsDef = false;
+ Op.IsImp = false;
+ Op.IsKill = false;
+ Op.IsDead = false;
Op.offset = 0;
return Op;
}
const MachineOperand &operator=(const MachineOperand &MO) {
contents = MO.contents;
IsDef = MO.IsDef;
+ IsImp = MO.IsImp;
+ IsKill = MO.IsKill;
+ IsDead = MO.IsDead;
opType = MO.opType;
offset = MO.offset;
return *this;
IsDef = true;
}
+ bool isImplicit() const {
+ assert(isRegister() && "Wrong MachineOperand accessor");
+ return IsImp;
+ }
+ void setImplicit() {
+ assert(isRegister() && "Wrong MachineOperand accessor");
+ IsImp = true;
+ }
+
+ bool isKill() const {
+ assert(isRegister() && "Wrong MachineOperand accessor");
+ return IsKill;
+ }
+ bool isDead() const {
+ assert(isRegister() && "Wrong MachineOperand accessor");
+ return IsDead;
+ }
+ void setIsKill() {
+ assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
+ IsKill = true;
+ }
+ void setIsDead() {
+ assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
+ IsDead = true;
+ }
+ void unsetIsKill() {
+ assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
+ IsKill = false;
+ }
+ void unsetIsDead() {
+ assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
+ IsDead = false;
+ }
+
/// getReg - Returns the register number.
///
unsigned getReg() const {
assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
contents.immedVal = Idx;
}
+ void setJumpTableIndex(unsigned Idx) {
+ assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
+ contents.immedVal = Idx;
+ }
/// isIdenticalTo - Return true if this operand is identical to the specified
- /// operand.
+ /// operand. Note: This method ignores isKill and isDead properties.
bool isIdenticalTo(const MachineOperand &Other) const;
/// ChangeToImmediate - Replace this operand with a new immediate operand of
opType = MO_Register;
contents.RegNo = Reg;
IsDef = isDef;
+ IsImp = false;
+ IsKill = false;
+ IsDead = false;
}
- friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
+ friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {
+ mop.print(os);
+ return os;
+ }
friend class MachineInstr;
};
/// MachineInstr - Representation of each machine instruction.
///
class MachineInstr {
- short Opcode; // the opcode
+ const TargetInstrDescriptor *TID; // Instruction descriptor.
+ unsigned short NumImplicitOps; // Number of implicit operands (which
+ // are determined at construction time).
+
std::vector<MachineOperand> Operands; // the operands
MachineInstr* prev, *next; // links for our intrusive list
MachineBasicBlock* parent; // pointer to the owning basic block
friend struct ilist_traits<MachineInstr>;
public:
- /// MachineInstr ctor - This constructor reserve's space for numOperand
- /// operands.
- MachineInstr(short Opcode, unsigned numOperands);
+ /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
+ /// TID NULL and no operands.
+ MachineInstr();
+
+ /// MachineInstr ctor - This constructor create a MachineInstr and add the
+ /// implicit operands. It reserves space for number of operands specified by
+ /// TargetInstrDescriptor.
+ MachineInstr(const TargetInstrDescriptor &TID);
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic
/// block.
///
- MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
+ MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
~MachineInstr();
const MachineBasicBlock* getParent() const { return parent; }
MachineBasicBlock* getParent() { return parent; }
+
+ /// getInstrDescriptor - Returns the target instruction descriptor of this
+ /// MachineInstr.
+ const TargetInstrDescriptor *getInstrDescriptor() const { return TID; }
/// getOpcode - Returns the opcode of this MachineInstr.
///
- const int getOpcode() const { return Opcode; }
+ const int getOpcode() const;
/// Access to explicit operands of the instruction.
///
delete removeFromParent();
}
+ /// findRegisterUseOperand() - Returns the MachineOperand that is a use of
+ /// the specific register or NULL if it is not found.
+ MachineOperand *findRegisterUseOperand(unsigned Reg);
+
+ /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
+ ///
+ void copyKillDeadInfo(const MachineInstr *MI);
+
//
// Debugging support
//
+ void print(std::ostream *OS, const TargetMachine *TM) const {
+ if (OS) print(*OS, TM);
+ }
void print(std::ostream &OS, const TargetMachine *TM) const;
+ void print(std::ostream &OS) const;
+ void print(std::ostream *OS) const { if (OS) print(*OS); }
void dump() const;
- friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
+ friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr){
+ minstr.print(os);
+ return os;
+ }
//===--------------------------------------------------------------------===//
// Accessors to add operands when building up machine instructions.
/// addRegOperand - Add a register operand.
///
- void addRegOperand(unsigned Reg, bool IsDef) {
- MachineOperand &Op = AddNewOperand();
+ void addRegOperand(unsigned Reg, bool IsDef, bool IsImp = false,
+ bool IsKill = false, bool IsDead = false) {
+ MachineOperand &Op = AddNewOperand(IsImp);
Op.opType = MachineOperand::MO_Register;
Op.IsDef = IsDef;
+ Op.IsImp = IsImp;
+ Op.IsKill = IsKill;
+ Op.IsDead = IsDead;
Op.contents.RegNo = Reg;
Op.offset = 0;
}
// Accessors used to modify instructions in place.
//
- /// setOpcode - Replace the opcode of the current instruction with a new one.
+ /// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
+ /// the current instruction with a new one.
///
- void setOpcode(unsigned Op) { Opcode = Op; }
+ void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
Operands.erase(Operands.begin()+i);
}
private:
- MachineOperand &AddNewOperand() {
- assert(!OperandsComplete() &&
+ MachineOperand &AddNewOperand(bool IsImp = false) {
+ assert((IsImp || !OperandsComplete()) &&
"Trying to add an operand to a machine instr that is already done!");
- Operands.push_back(MachineOperand());
- return Operands.back();
- }
+ if (NumImplicitOps == 0) { // This is true most of the time.
+ Operands.push_back(MachineOperand());
+ return Operands.back();
+ } else {
+ return *Operands.insert(Operands.begin()+Operands.size()-NumImplicitOps,
+ MachineOperand());
+ }
+ }
+
+ /// addImplicitDefUseOperands - Add all implicit def and use operands to
+ /// this instruction.
+ void addImplicitDefUseOperands();
};
//===----------------------------------------------------------------------===//
projects / oota-llvm.git / blobdiff