//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the declaration of the MachineInstr class, which is the
typedef short MachineOpCode;
//===----------------------------------------------------------------------===//
-// class MachineOperand
-//
+// class MachineOperand
+//
// Purpose:
// Representation of each machine instruction operand.
// This class is designed so that you can allocate a vector of operands
// first and initialize each one later.
//
// E.g, for this VM instruction:
-// ptr = alloca type, numElements
+// ptr = alloca type, numElements
// we generate 2 machine instructions on the SPARC:
-//
-// mul Constant, Numelements -> Reg
-// add %sp, Reg -> Ptr
-//
+//
+// mul Constant, Numelements -> Reg
+// add %sp, Reg -> Ptr
+//
// Each instruction has 3 operands, listed above. Of those:
-// - Reg, NumElements, and Ptr are of operand type MO_Register.
-// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
-//
+// - Reg, NumElements, and Ptr are of operand type MO_Register.
+// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
+//
// For the register operands, the virtual register type is as follows:
-//
-// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
-// MachineInstr* minstr will point to the instruction that computes reg.
-//
-// - %sp will be of virtual register type MO_MachineReg.
-// The field regNum identifies the machine register.
-//
-// - NumElements will be of virtual register type MO_VirtualReg.
-// The field Value* value identifies the value.
-//
-// - Ptr will also be of virtual register type MO_VirtualReg.
-// Again, the field Value* value identifies the value.
-//
+//
+// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
+// MachineInstr* minstr will point to the instruction that computes reg.
+//
+// - %sp will be of virtual register type MO_MachineReg.
+// The field regNum identifies the machine register.
+//
+// - NumElements will be of virtual register type MO_VirtualReg.
+// The field Value* value identifies the value.
+//
+// - Ptr will also be of virtual register type MO_VirtualReg.
+// Again, the field Value* value identifies the value.
+//
//===----------------------------------------------------------------------===//
struct MachineOperand {
LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
- PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
+ PCRELATIVE = 0x40 // Operand is relative to PC, not a global address
};
public:
};
enum MachineOperandType {
- MO_VirtualRegister, // virtual register for *value
- MO_MachineRegister, // pre-assigned machine register `regNum'
+ MO_VirtualRegister, // virtual register for *value
+ MO_MachineRegister, // pre-assigned machine register `regNum'
MO_CCRegister,
MO_SignExtendedImmed,
MO_UnextendedImmed,
MO_FrameIndex, // Abstract Stack Frame Index
MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
MO_ExternalSymbol, // Name of external global symbol
- MO_GlobalAddress, // Address of a global value
+ MO_GlobalAddress // Address of a global value
};
-
+
private:
union {
Value* value; // BasicBlockVal for a label operand.
// ConstantVal for a non-address immediate.
// Virtual register for an SSA operand,
// including hidden operands required for
- // the generated machine code.
+ // the generated machine code.
// LLVM global for MO_GlobalAddress.
- int64_t immedVal; // Constant value for an explicit constant
+ int64_t immedVal; // Constant value for an explicit constant
MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
const char *SymbolName; // For MO_ExternalSymbol type
char flags; // see bit field definitions above
MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
union {
- int regNum; // register number for an explicit register
+ int regNum; // register number for an explicit register
// will be set for a value after reg allocation
int offset; // Offset to address of global or external, only
- // valid for MO_GlobalAddress and MO_ExternalSym
+ // valid for MO_GlobalAddress, MO_ExternalSym
+ // and MO_ConstantPoolIndex
} extra;
- void zeroContents () {
+ void zeroContents () {
memset (&contents, 0, sizeof (contents));
memset (&extra, 0, sizeof (extra));
}
MachineOperand(int64_t ImmVal = 0,
- MachineOperandType OpTy = MO_VirtualRegister)
+ MachineOperandType OpTy = MO_VirtualRegister, int Offset = 0)
: flags(0), opType(OpTy) {
zeroContents ();
contents.immedVal = ImmVal;
- extra.regNum = -1;
+ if (OpTy == MachineOperand::MO_ConstantPoolIndex)
+ extra.offset = Offset;
+ else
+ extra.regNum = -1;
}
MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy)
}
MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
- bool isPCRelative = false)
+ bool isPCRelative = false)
: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
assert(OpTy != MachineOperand::MO_GlobalAddress);
zeroContents();
}
MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy,
- bool isPCRelative = false, int Offset = 0)
+ bool isPCRelative = false, int Offset = 0)
: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
assert(OpTy == MachineOperand::MO_GlobalAddress);
zeroContents ();
extra = M.extra;
}
-
+
~MachineOperand() {}
-
+
const MachineOperand &operator=(const MachineOperand &MO) {
contents = MO.contents;
flags = MO.flags;
}
/// getType - Returns the MachineOperandType for this operand.
- ///
+ ///
MachineOperandType getType() const { return opType; }
/// getUseType - Returns the MachineOperandUseType of this operand.
/// has one. This is deprecated and only used by the SPARC v9 backend.
///
Value* getVRegValueOrNull() const {
- return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
isPCRelativeDisp()) ? contents.value : NULL;
}
return (GlobalValue*)contents.value;
}
int getOffset() const {
- assert((isGlobalAddress() || isExternalSymbol()) &&
+ assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
"Wrong MachineOperand accessor");
return extra.offset;
}
///
bool hasAllocatedReg() const {
return (extra.regNum >= 0 &&
- (opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ (opType == MO_VirtualRegister || opType == MO_CCRegister ||
opType == MO_MachineRegister));
}
// code.' It's not clear where the duplication is.
assert(hasAllocatedReg() && "This operand cannot have a register number!");
extra.regNum = Reg;
- }
+ }
void setValueReg(Value *val) {
assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*");
contents.value = val;
}
-
+
void setImmedValue(int immVal) {
assert(isImmediate() && "Wrong MachineOperand mutator");
contents.immedVal = immVal;
}
void setOffset(int Offset) {
- assert((isGlobalAddress() || isExternalSymbol()) &&
+ assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
"Wrong MachineOperand accessor");
extra.offset = Offset;
}
void markLo32() { flags |= LOFLAG32; }
void markHi64() { flags |= HIFLAG64; }
void markLo64() { flags |= LOFLAG64; }
-
+
private:
/// setRegForValue - Replaces the Value with its corresponding physical
/// register after register allocation is complete. This is deprecated
/// and only used by the SPARC v9 back-end.
///
void setRegForValue(int reg) {
- assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
- opType == MO_MachineRegister);
+ assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
+ opType == MO_MachineRegister);
extra.regNum = reg;
}
-
+
friend class MachineInstr;
};
//===----------------------------------------------------------------------===//
-// class MachineInstr
-//
+// class MachineInstr
+//
// Purpose:
// Representation of each machine instruction.
-//
+//
// MachineOpCode must be an enum, defined separately for each target.
// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
-//
+//
// There are 2 kinds of operands:
-//
-// (1) Explicit operands of the machine instruction in vector operands[]
-//
+//
+// (1) Explicit operands of the machine instruction in vector operands[]
+//
// (2) "Implicit operands" are values implicitly used or defined by the
// machine instruction, such as arguments to a CALL, return value of
// a CALL (if any), and return value of a RETURN.
/// block.
///
MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
-
+
~MachineInstr();
const MachineBasicBlock* getParent() const { return parent; }
/// Access to explicit operands of the instruction.
///
unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
-
+
const MachineOperand& getOperand(unsigned i) const {
assert(i < getNumOperands() && "getOperand() out of range!");
return operands[i];
// This returns the i'th entry in the operand vector.
// That represents the i'th explicit operand or the (i-N)'th implicit operand,
// depending on whether i < N or i >= N.
- //
+ //
const MachineOperand& getExplOrImplOperand(unsigned i) const {
assert(i < operands.size() && "getExplOrImplOperand() out of range!");
return (i < getNumOperands()? getOperand(i)
//
// Access to implicit operands of the instruction
- //
+ //
unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
-
+
MachineOperand& getImplicitOp(unsigned i) {
assert(i < numImplicitRefs && "implicit ref# out of range!");
return operands[i + operands.size() - numImplicitRefs];
void dump() const;
friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
- //
// Define iterators to access the Value operands of the Machine Instruction.
// Note that these iterators only enumerate the explicit operands.
- // begin() and end() are defined to produce these iterators...
+ // begin() and end() are defined to produce these iterators. NOTE, these are
+ // SparcV9 specific!
//
template<class _MI, class _V> class ValOpIterator;
typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
/// addConstantPoolndexOperand - Add a constant pool object index to the
/// instruction.
///
- void addConstantPoolIndexOperand(unsigned I) {
+ void addConstantPoolIndexOperand(unsigned I, int Offset=0) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
/// replace - Support to rewrite a machine instruction in place: for now,
/// simply replace() and then set new operands with Set.*Operand methods
/// below.
- ///
+ ///
void replace(short Opcode, unsigned numOperands);
/// setOpcode - Replace the opcode of the current instruction with a new one.
}
// Access to set the operands when building the machine instruction
- //
+ //
void SetMachineOperandVal(unsigned i,
MachineOperand::MachineOperandType operandType,
Value* V);
unsigned substituteValue(const Value* oldVal, Value* newVal,
bool defsOnly, bool notDefsAndUses,
bool& someArgsWereIgnored);
-
+
// SetRegForOperand -
// SetRegForImplicitRef -
// Mark an explicit or implicit operand with its allocated physical register.
- //
+ //
void SetRegForOperand(unsigned i, int regNum);
void SetRegForImplicitRef(unsigned i, int regNum);
//
- // Iterator to enumerate machine operands.
- //
+ // Iterator to enumerate machine operands. NOTE, this is SPARCV9 specific!
+ //
template<class MITy, class VTy>
class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
unsigned i;
MITy MI;
-
+
void skipToNextVal() {
while (i < MI->getNumOperands() &&
!( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
&& MI->getOperand(i).getVRegValue() != 0))
++i;
}
-
+
inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
skipToNextVal();
}
-
+
public:
typedef ValOpIterator<MITy, VTy> _Self;
-
+
inline VTy operator*() const {
return MI->getOperand(i).getVRegValue();
}
inline VTy operator->() const { return operator*(); }
- inline bool isUse() const { return MI->getOperand(i).isUse(); }
- inline bool isDef() const { return MI->getOperand(i).isDef(); }
+ inline bool isUse() const { return MI->getOperand(i).isUse(); }
+ inline bool isDef() const { return MI->getOperand(i).isDef(); }
inline _Self& operator++() { i++; skipToNextVal(); return *this; }
inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
- inline bool operator==(const _Self &y) const {
+ inline bool operator==(const _Self &y) const {
return i == y.i;
}
- inline bool operator!=(const _Self &y) const {
+ inline bool operator!=(const _Self &y) const {
return !operator==(y);
}
}
};
- // define begin() and end()
+ // Note: These are Sparc-V9 specific!
val_op_iterator begin() { return val_op_iterator::begin(this); }
val_op_iterator end() { return val_op_iterator::end(this); }
-
const_val_op_iterator begin() const {
return const_val_op_iterator::begin(this);
}
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