Reference RegionPass to stop it being eliminated.

[oota-llvm.git] / include / llvm / CodeGen / MachineInstr.h

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 08ada4cc91c06cf0e1c4952cb07205ce93d23d25..fc84f8c9531328095c6a658b128015887d5aab79 100644 (file)
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -201,12 +201,14 @@ public:
   /// isLabel - Returns true if the MachineInstr represents a label.
   ///
   bool isLabel() const {
-    return getOpcode() == TargetOpcode::DBG_LABEL ||
+    return getOpcode() == TargetOpcode::PROLOG_LABEL ||
            getOpcode() == TargetOpcode::EH_LABEL ||
            getOpcode() == TargetOpcode::GC_LABEL;
   }
   
-  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
+  bool isPrologLabel() const {
+    return getOpcode() == TargetOpcode::PROLOG_LABEL;
+  }
   bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
   bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
   bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
@@ -215,9 +217,6 @@ public:
   bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
   bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
   bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
-  bool isExtractSubreg() const {
-    return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
-  }
   bool isInsertSubreg() const {
     return getOpcode() == TargetOpcode::INSERT_SUBREG;
   }
@@ -234,7 +233,13 @@ public:
   /// isCopyLike - Return true if the instruction behaves like a copy.
   /// This does not include native copy instructions.
   bool isCopyLike() const {
-    return isCopy() || isSubregToReg() || isExtractSubreg() || isInsertSubreg();
+    return isCopy() || isSubregToReg();
+  }
+
+  /// isIdentityCopy - Return true is the instruction is an identity copy.
+  bool isIdentityCopy() const {
+    return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
+      getOperand(0).getSubReg() == getOperand(1).getSubReg();
   }
 
   /// readsRegister - Return true if the MachineInstr reads the specified
@@ -411,6 +416,10 @@ public:
   ///
   bool allDefsAreDead() const;
 
+  /// copyImplicitOps - Copy implicit register operands from specified
+  /// instruction to this instruction.
+  void copyImplicitOps(const MachineInstr *MI);
+
   //
   // Debugging support
   //