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[oota-llvm.git] / include / llvm / CodeGen / MachineRegisterInfo.h

diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h
index b851fdf66da9496d27bb402c6330b276d9afbc1a..80c37b39ca0ca26536c9cb211f2a2b4287c875ac 100644 (file)
--- a/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -32,6 +32,20 @@ class MachineRegisterInfo {
   /// Each element in this list contains the register class of the vreg and the
   /// start of the use/def list for the register.
   std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
+
+  /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
+  /// virtual registers. For each target register class, it keeps a list of
+  /// virtual registers belonging to the class.
+  std::vector<std::vector<unsigned> > RegClass2VRegMap;
+
+  /// RegAllocHints - This vector records register allocation hints for virtual
+  /// registers. For each virtual register, it keeps a register and hint type
+  /// pair making up the allocation hint. Hint type is target specific except
+  /// for the value 0 which means the second value of the pair is the preferred
+  /// register for allocation. For example, if the hint is <0, 1024>, it means
+  /// the allocator should prefer the physical register allocated to the virtual
+  /// register of the hint.
+  std::vector<std::pair<unsigned, unsigned> > RegAllocHints;
   
   /// PhysRegUseDefLists - This is an array of the head of the use/def list for
   /// physical registers.
@@ -76,6 +90,10 @@ public:
   }
   static reg_iterator reg_end() { return reg_iterator(0); }
 
+  /// reg_empty - Return true if there are no instructions using or defining the
+  /// specified register (it may be live-in).
+  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
+
   /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
   typedef defusechain_iterator<false,true> def_iterator;
   def_iterator def_begin(unsigned RegNo) const {
@@ -83,6 +101,10 @@ public:
   }
   static def_iterator def_end() { return def_iterator(0); }
 
+  /// def_empty - Return true if there are no instructions defining the
+  /// specified register (it may be live-in).
+  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
+
   /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
   typedef defusechain_iterator<true,false> use_iterator;
   use_iterator use_begin(unsigned RegNo) const {
@@ -130,6 +152,7 @@ public:
   //===--------------------------------------------------------------------===//
   
   /// getRegClass - Return the register class of the specified virtual register.
+  ///
   const TargetRegisterClass *getRegClass(unsigned Reg) const {
     Reg -= TargetRegisterInfo::FirstVirtualRegister;
     assert(Reg < VRegInfo.size() && "Invalid vreg!");
@@ -137,36 +160,44 @@ public:
   }
 
   /// setRegClass - Set the register class of the specified virtual register.
-  void setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
-    Reg -= TargetRegisterInfo::FirstVirtualRegister;
-    assert(Reg < VRegInfo.size() && "Invalid vreg!");
-    VRegInfo[Reg].first = RC;
-  }
-  
+  ///
+  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
+
   /// createVirtualRegister - Create and return a new virtual register in the
   /// function with the specified register class.
   ///
-  unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
-    assert(RegClass && "Cannot create register without RegClass!");
-    // Add a reg, but keep track of whether the vector reallocated or not.
-    void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
-    VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
-    
-    if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)
-      return getLastVirtReg();
-
-    // Otherwise, the vector reallocated, handle this now.
-    HandleVRegListReallocation();
-    return getLastVirtReg();
-  }
+  unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
 
   /// getLastVirtReg - Return the highest currently assigned virtual register.
   ///
   unsigned getLastVirtReg() const {
     return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
   }
-  
-  
+
+  /// getRegClassVirtRegs - Return the list of virtual registers of the given
+  /// target register class.
+  std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
+    return RegClass2VRegMap[RC->getID()];
+  }
+
+  /// setRegAllocationHint - Specify a register allocation hint for the
+  /// specified virtual register.
+  void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
+    Reg -= TargetRegisterInfo::FirstVirtualRegister;
+    assert(Reg < VRegInfo.size() && "Invalid vreg!");
+    RegAllocHints[Reg].first  = Type;
+    RegAllocHints[Reg].second = PrefReg;
+  }
+
+  /// getRegAllocationHint - Return the register allocation hint for the
+  /// specified virtual register.
+  std::pair<unsigned, unsigned>
+  getRegAllocationHint(unsigned Reg) const {
+    Reg -= TargetRegisterInfo::FirstVirtualRegister;
+    assert(Reg < VRegInfo.size() && "Invalid vreg!");
+    return RegAllocHints[Reg];
+  }
+
   //===--------------------------------------------------------------------===//
   // Physical Register Use Info
   //===--------------------------------------------------------------------===//