improve comments.

[oota-llvm.git] / include / llvm / CodeGen / MachineRegisterInfo.h

diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h
index f477e86554e2be6b443aceb6170b69b7a7bd1f0d..80c37b39ca0ca26536c9cb211f2a2b4287c875ac 100644 (file)
--- a/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -37,6 +37,15 @@ class MachineRegisterInfo {
   /// virtual registers. For each target register class, it keeps a list of
   /// virtual registers belonging to the class.
   std::vector<std::vector<unsigned> > RegClass2VRegMap;
+
+  /// RegAllocHints - This vector records register allocation hints for virtual
+  /// registers. For each virtual register, it keeps a register and hint type
+  /// pair making up the allocation hint. Hint type is target specific except
+  /// for the value 0 which means the second value of the pair is the preferred
+  /// register for allocation. For example, if the hint is <0, 1024>, it means
+  /// the allocator should prefer the physical register allocated to the virtual
+  /// register of the hint.
+  std::vector<std::pair<unsigned, unsigned> > RegAllocHints;
   
   /// PhysRegUseDefLists - This is an array of the head of the use/def list for
   /// physical registers.
@@ -81,6 +90,10 @@ public:
   }
   static reg_iterator reg_end() { return reg_iterator(0); }
 
+  /// reg_empty - Return true if there are no instructions using or defining the
+  /// specified register (it may be live-in).
+  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
+
   /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
   typedef defusechain_iterator<false,true> def_iterator;
   def_iterator def_begin(unsigned RegNo) const {
@@ -88,6 +101,10 @@ public:
   }
   static def_iterator def_end() { return def_iterator(0); }
 
+  /// def_empty - Return true if there are no instructions defining the
+  /// specified register (it may be live-in).
+  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
+
   /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
   typedef defusechain_iterator<true,false> use_iterator;
   use_iterator use_begin(unsigned RegNo) const {
@@ -144,23 +161,8 @@ public:
 
   /// setRegClass - Set the register class of the specified virtual register.
   ///
-  void setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
-    unsigned VR = Reg;
-    Reg -= TargetRegisterInfo::FirstVirtualRegister;
-    assert(Reg < VRegInfo.size() && "Invalid vreg!");
-    const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
-    VRegInfo[Reg].first = RC;
+  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
 
-    // Remove from old register class's vregs list. This may be slow but
-    // fortunately this operation is rarely needed.
-    std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
-    std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
-    VRegs.erase(I);
-
-    // Add to new register class's vregs list.
-    RegClass2VRegMap[RC->getID()].push_back(VR);
-  }
-  
   /// createVirtualRegister - Create and return a new virtual register in the
   /// function with the specified register class.
   ///
@@ -177,7 +179,25 @@ public:
   std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
     return RegClass2VRegMap[RC->getID()];
   }
-  
+
+  /// setRegAllocationHint - Specify a register allocation hint for the
+  /// specified virtual register.
+  void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
+    Reg -= TargetRegisterInfo::FirstVirtualRegister;
+    assert(Reg < VRegInfo.size() && "Invalid vreg!");
+    RegAllocHints[Reg].first  = Type;
+    RegAllocHints[Reg].second = PrefReg;
+  }
+
+  /// getRegAllocationHint - Return the register allocation hint for the
+  /// specified virtual register.
+  std::pair<unsigned, unsigned>
+  getRegAllocationHint(unsigned Reg) const {
+    Reg -= TargetRegisterInfo::FirstVirtualRegister;
+    assert(Reg < VRegInfo.size() && "Invalid vreg!");
+    return RegAllocHints[Reg];
+  }
+
   //===--------------------------------------------------------------------===//
   // Physical Register Use Info
   //===--------------------------------------------------------------------===//