Rename some GC classes so that their roll will hopefully be clearer.

[oota-llvm.git] / include / llvm / CodeGen / MachineRegisterInfo.h

diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h
index 5b84922b554c3d878b81039a784009df879a2436..b851fdf66da9496d27bb402c6330b276d9afbc1a 100644 (file)
--- a/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -16,13 +16,14 @@
 
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/iterator"
+#include "llvm/ADT/iterator.h"
 #include <vector>
 
 namespace llvm {
   
-/// MachineRegisterInfo - Keep track of information for each virtual register,
-/// including its register class.
+/// MachineRegisterInfo - Keep track of information for virtual and physical
+/// registers, including vreg register classes, use/def chains for registers,
+/// etc.
 class MachineRegisterInfo {
   /// VRegInfo - Information we keep for each virtual register.  The entries in
   /// this vector are actually converted to vreg numbers by adding the 
@@ -89,6 +90,10 @@ public:
   }
   static use_iterator use_end() { return use_iterator(0); }
   
+  /// use_empty - Return true if there are no instructions using the specified
+  /// register.
+  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
+
   
   /// replaceRegWith - Replace all instances of FromReg with ToReg in the
   /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
@@ -110,17 +115,33 @@ public:
     RegNo -= TargetRegisterInfo::FirstVirtualRegister;
     return VRegInfo[RegNo].second;
   }
+
+  /// getVRegDef - Return the machine instr that defines the specified virtual
+  /// register or null if none is found.  This assumes that the code is in SSA
+  /// form, so there should only be one definition.
+  MachineInstr *getVRegDef(unsigned Reg) const;
+  
+#ifndef NDEBUG
+  void dumpUses(unsigned RegNo) const;
+#endif
   
   //===--------------------------------------------------------------------===//
   // Virtual Register Info
   //===--------------------------------------------------------------------===//
   
   /// getRegClass - Return the register class of the specified virtual register.
-  const TargetRegisterClass *getRegClass(unsigned Reg) {
+  const TargetRegisterClass *getRegClass(unsigned Reg) const {
     Reg -= TargetRegisterInfo::FirstVirtualRegister;
     assert(Reg < VRegInfo.size() && "Invalid vreg!");
     return VRegInfo[Reg].first;
   }
+
+  /// setRegClass - Set the register class of the specified virtual register.
+  void setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
+    Reg -= TargetRegisterInfo::FirstVirtualRegister;
+    assert(Reg < VRegInfo.size() && "Invalid vreg!");
+    VRegInfo[Reg].first = RC;
+  }
   
   /// createVirtualRegister - Create and return a new virtual register in the
   /// function with the specified register class.
@@ -142,14 +163,9 @@ public:
   /// getLastVirtReg - Return the highest currently assigned virtual register.
   ///
   unsigned getLastVirtReg() const {
-    return VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
+    return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
   }
   
-  /// getVRegDef - Return the machine instr that defines the specified virtual
-  /// register or null if none is found.  This assumes that the code is in SSA
-  /// form, so there should only be one definition.
-  MachineInstr *getVRegDef(unsigned Reg) const;
-  
   
   //===--------------------------------------------------------------------===//
   // Physical Register Use Info
@@ -190,6 +206,14 @@ public:
   liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
   liveout_iterator liveout_end()   const { return LiveOuts.end(); }
   bool             liveout_empty() const { return LiveOuts.empty(); }
+
+  bool isLiveIn(unsigned Reg) const {
+    for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
+      if (I->first == Reg || I->second == Reg)
+        return true;
+    return false;
+  }
+
 private:
   void HandleVRegListReallocation();
   
@@ -207,8 +231,8 @@ public:
       // If the first node isn't one we're interested in, advance to one that
       // we are interested in.
       if (op) {
-        if (!ReturnUses && op->isUse() || 
-            !ReturnDefs && op->isDef())
+        if ((!ReturnUses && op->isUse()) ||
+            (!ReturnDefs && op->isDef()))
           ++*this;
       }
     }
@@ -236,8 +260,8 @@ public:
       Op = Op->getNextOperandForReg();
       
       // If this is an operand we don't care about, skip it.
-      while (Op && (!ReturnUses && Op->isUse() || 
-                    !ReturnDefs && Op->isDef()))
+      while (Op && ((!ReturnUses && Op->isUse()) || 
+                    (!ReturnDefs && Op->isDef())))
         Op = Op->getNextOperandForReg();
       
       return *this;