#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/iterator.h"
#include <vector>
namespace llvm {
/// Each element in this list contains the register class of the vreg and the
/// start of the use/def list for the register.
std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
+
+ /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
+ /// virtual registers. For each target register class, it keeps a list of
+ /// virtual registers belonging to the class.
+ std::vector<std::vector<unsigned> > RegClass2VRegMap;
+
+ /// RegAllocHints - This vector records register allocation hints for virtual
+ /// registers. For each virtual register, it keeps a register and hint type
+ /// pair making up the allocation hint. Hint type is target specific except
+ /// for the value 0 which means the second value of the pair is the preferred
+ /// register for allocation. For example, if the hint is <0, 1024>, it means
+ /// the allocator should prefer the physical register allocated to the virtual
+ /// register of the hint.
+ std::vector<std::pair<unsigned, unsigned> > RegAllocHints;
/// PhysRegUseDefLists - This is an array of the head of the use/def list for
/// physical registers.
/// reg_begin/reg_end - Provide iteration support to walk over all definitions
/// and uses of a register within the MachineFunction that corresponds to this
/// MachineRegisterInfo object.
- template<bool Uses, bool Defs>
+ template<bool Uses, bool Defs, bool SkipDebug>
class defusechain_iterator;
/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
/// register.
- typedef defusechain_iterator<true,true> reg_iterator;
+ typedef defusechain_iterator<true,true,false> reg_iterator;
reg_iterator reg_begin(unsigned RegNo) const {
return reg_iterator(getRegUseDefListHead(RegNo));
}
static reg_iterator reg_end() { return reg_iterator(0); }
+ /// reg_empty - Return true if there are no instructions using or defining the
+ /// specified register (it may be live-in).
+ bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
+
/// def_iterator/def_begin/def_end - Walk all defs of the specified register.
- typedef defusechain_iterator<false,true> def_iterator;
+ typedef defusechain_iterator<false,true,false> def_iterator;
def_iterator def_begin(unsigned RegNo) const {
return def_iterator(getRegUseDefListHead(RegNo));
}
static def_iterator def_end() { return def_iterator(0); }
+ /// def_empty - Return true if there are no instructions defining the
+ /// specified register (it may be live-in).
+ bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
+
/// use_iterator/use_begin/use_end - Walk all uses of the specified register.
- typedef defusechain_iterator<true,false> use_iterator;
+ typedef defusechain_iterator<true,false,false> use_iterator;
use_iterator use_begin(unsigned RegNo) const {
return use_iterator(getRegUseDefListHead(RegNo));
}
/// register.
bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
+ /// hasOneUse - Return true if there is exactly one instruction using the
+ /// specified register.
+ bool hasOneUse(unsigned RegNo) const;
+
+ /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
+ /// specified register, skipping those marked as Debug.
+ typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
+ use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
+ return use_nodbg_iterator(getRegUseDefListHead(RegNo));
+ }
+ static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
+ /// use_nodbg_empty - Return true if there are no non-Debug instructions
+ /// using the specified register.
+ bool use_nodbg_empty(unsigned RegNo) const {
+ return use_nodbg_begin(RegNo) == use_nodbg_end();
+ }
+
+ /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
+ /// instruction using the specified register.
+ bool hasOneNonDBGUse(unsigned RegNo) const;
+
/// replaceRegWith - Replace all instances of FromReg with ToReg in the
/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
/// except that it also changes any definitions of the register as well.
//===--------------------------------------------------------------------===//
/// getRegClass - Return the register class of the specified virtual register.
+ ///
const TargetRegisterClass *getRegClass(unsigned Reg) const {
Reg -= TargetRegisterInfo::FirstVirtualRegister;
assert(Reg < VRegInfo.size() && "Invalid vreg!");
}
/// setRegClass - Set the register class of the specified virtual register.
- void setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
- Reg -= TargetRegisterInfo::FirstVirtualRegister;
- assert(Reg < VRegInfo.size() && "Invalid vreg!");
- VRegInfo[Reg].first = RC;
- }
-
+ ///
+ void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
+
/// createVirtualRegister - Create and return a new virtual register in the
/// function with the specified register class.
///
- unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
- assert(RegClass && "Cannot create register without RegClass!");
- // Add a reg, but keep track of whether the vector reallocated or not.
- void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
- VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
-
- if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)
- return getLastVirtReg();
-
- // Otherwise, the vector reallocated, handle this now.
- HandleVRegListReallocation();
- return getLastVirtReg();
- }
+ unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
/// getLastVirtReg - Return the highest currently assigned virtual register.
///
unsigned getLastVirtReg() const {
return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
}
-
-
+
+ /// getRegClassVirtRegs - Return the list of virtual registers of the given
+ /// target register class.
+ std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
+ return RegClass2VRegMap[RC->getID()];
+ }
+
+ /// setRegAllocationHint - Specify a register allocation hint for the
+ /// specified virtual register.
+ void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
+ Reg -= TargetRegisterInfo::FirstVirtualRegister;
+ assert(Reg < VRegInfo.size() && "Invalid vreg!");
+ RegAllocHints[Reg].first = Type;
+ RegAllocHints[Reg].second = PrefReg;
+ }
+
+ /// getRegAllocationHint - Return the register allocation hint for the
+ /// specified virtual register.
+ std::pair<unsigned, unsigned>
+ getRegAllocationHint(unsigned Reg) const {
+ Reg -= TargetRegisterInfo::FirstVirtualRegister;
+ assert(Reg < VRegInfo.size() && "Invalid vreg!");
+ return RegAllocHints[Reg];
+ }
+
//===--------------------------------------------------------------------===//
// Physical Register Use Info
//===--------------------------------------------------------------------===//
liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
liveout_iterator liveout_end() const { return LiveOuts.end(); }
bool liveout_empty() const { return LiveOuts.empty(); }
+
+ bool isLiveIn(unsigned Reg) const;
+ bool isLiveOut(unsigned Reg) const;
+
+ /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
+ /// into the given entry block.
+ void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
+ const TargetRegisterInfo &TRI,
+ const TargetInstrInfo &TII);
+
private:
void HandleVRegListReallocation();
/// operands in the function that use or define a specific register. If
/// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
/// returns defs. If neither are true then you are silly and it always
- /// returns end().
- template<bool ReturnUses, bool ReturnDefs>
+ /// returns end(). If SkipDebug is true it skips uses marked Debug
+ /// when incrementing.
+ template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
class defusechain_iterator
- : public forward_iterator<MachineInstr, ptrdiff_t> {
+ : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
MachineOperand *Op;
explicit defusechain_iterator(MachineOperand *op) : Op(op) {
// If the first node isn't one we're interested in, advance to one that
// we are interested in.
if (op) {
if ((!ReturnUses && op->isUse()) ||
- (!ReturnDefs && op->isDef()))
+ (!ReturnDefs && op->isDef()) ||
+ (SkipDebug && op->isDebug()))
++*this;
}
}
friend class MachineRegisterInfo;
public:
- typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference;
- typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer;
+ typedef std::iterator<std::forward_iterator_tag,
+ MachineInstr, ptrdiff_t>::reference reference;
+ typedef std::iterator<std::forward_iterator_tag,
+ MachineInstr, ptrdiff_t>::pointer pointer;
defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
defusechain_iterator() : Op(0) {}
// If this is an operand we don't care about, skip it.
while (Op && ((!ReturnUses && Op->isUse()) ||
- (!ReturnDefs && Op->isDef())))
+ (!ReturnDefs && Op->isDef()) ||
+ (SkipDebug && Op->isDebug())))
Op = Op->getNextOperandForReg();
return *this;