class FunctionPass;
class MachineFunctionPass;
class PassInfo;
+ class PassManagerBase;
class TargetLowering;
class TargetRegisterClass;
class raw_ostream;
namespace llvm {
-extern char &NoPassID; // Allow targets to choose not to run a pass.
-
class PassConfigImpl;
/// Target-Independent Code Generator Pass Configuration Options.
/// optimization after regalloc.
static char PostRAMachineLICMID;
+private:
+ PassManagerBase *PM;
+ AnalysisID StartAfter;
+ AnalysisID StopAfter;
+ bool Started;
+ bool Stopped;
+
protected:
TargetMachine *TM;
- PassManagerBase *PM;
PassConfigImpl *Impl; // Internal data structures
bool Initialized; // Flagged after all passes are configured.
CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
+ /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
+ /// running only a portion of the normal code-gen pass sequence. If the
+ /// Start pass ID is zero, then compilation will begin at the normal point;
+ /// otherwise, clear the Started flag to indicate that passes should not be
+ /// added until the starting pass is seen. If the Stop pass ID is zero,
+ /// then compilation will continue to the end.
+ void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
+ StartAfter = Start;
+ StopAfter = Stop;
+ Started = (StartAfter == 0);
+ }
+
void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
bool getEnableTailMerge() const { return EnableTailMerge; }
/// Allow the target to override a specific pass without overriding the pass
/// pipeline. When passes are added to the standard pipeline at the
- /// point where StadardID is expected, add TargetID in its place.
- void substitutePass(char &StandardID, char &TargetID);
+ /// point where StandardID is expected, add TargetID in its place.
+ void substitutePass(AnalysisID StandardID, AnalysisID TargetID);
/// Insert InsertedPassID pass after TargetPassID pass.
- void insertPass(const char &TargetPassID, const char &InsertedPassID);
+ void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID);
/// Allow the target to enable a specific standard pass by default.
- void enablePass(char &ID) { substitutePass(ID, ID); }
+ void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
/// Allow the target to disable a specific standard pass by default.
- void disablePass(char &ID) { substitutePass(ID, NoPassID); }
+ void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); }
- /// Return the pass ssubtituted for StandardID by the target.
+ /// Return the pass substituted for StandardID by the target.
/// If no substitution exists, return StandardID.
AnalysisID getPassSubstitution(AnalysisID StandardID) const;
/// transforms following machine independent optimization.
virtual void addIRPasses();
+ /// Add passes to lower exception handling for the code generator.
+ void addPassesToHandleExceptions();
+
/// Add common passes that perform LLVM IR to IR transforms in preparation for
/// instruction selection.
virtual void addISelPrepare();
/// LLVMTargetMachine provides standard regalloc passes for most targets.
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
+ /// addPreRewrite - Add passes to the optimized register allocation pipeline
+ /// after register allocation is complete, but before virtual registers are
+ /// rewritten to physical registers.
+ ///
+ /// These passes must preserve VirtRegMap and LiveIntervals, and when running
+ /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
+ /// When these passes run, VirtRegMap contains legal physreg assignments for
+ /// all virtual registers.
+ virtual bool addPreRewrite() {
+ return false;
+ }
+
/// addFinalizeRegAlloc - This method may be implemented by targets that want
/// to run passes within the regalloc pipeline, immediately after the register
/// allocation pass itself. These passes run as soon as virtual regisiters
///
/// Add a CodeGen pass at this point in the pipeline after checking overrides.
- /// Return the pass that was added, or NoPassID.
- AnalysisID addPass(char &ID);
+ /// Return the pass that was added, or zero if no pass was added.
+ AnalysisID addPass(AnalysisID PassID);
+
+ /// Add a pass to the PassManager if that pass is supposed to be run, as
+ /// determined by the StartAfter and StopAfter options.
+ void addPass(Pass *P);
/// addMachinePasses helper to create the target-selected or overriden
/// regalloc pass.
/// printAndVerify - Add a pass to dump then verify the machine function, if
/// those steps are enabled.
///
- void printAndVerify(const char *Banner) const;
+ void printAndVerify(const char *Banner);
};
} // namespace llvm
/// into tails of their predecessors.
extern char &TailDuplicateID;
+ /// MachineTraceMetrics - This pass computes critical path and CPU resource
+ /// usage in an ensemble of traces.
+ extern char &MachineTraceMetricsID;
+
+ /// EarlyIfConverter - This pass performs if-conversion on SSA form by
+ /// inserting cmov instructions.
+ extern char &EarlyIfConverterID;
+
/// IfConverter - This pass performs machine code if conversion.
extern char &IfConverterID;