Initial support for carrying MachineInstrs in SUnits.

[oota-llvm.git] / include / llvm / CodeGen / ScheduleDAG.h

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index bca571273791eff82ab02bc2ad107ae3e1bc0f03..125f8eaa8cefba552fe7c505813e586f07321282 100644 (file)
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -92,8 +92,10 @@ namespace llvm {
   /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
   /// a group of nodes flagged together.
   struct SUnit {
+  private:
     SDNode *Node;                       // Representative node.
-    SmallVector<SDNode*,4> FlaggedNodes;// All nodes flagged to Node.
+    MachineInstr *Instr;                // Alternatively, a MachineInstr.
+  public:
     SUnit *OrigNode;                    // If not this, the node from which
                                         // this node was cloned.
     
@@ -110,8 +112,8 @@ namespace llvm {
     unsigned NodeNum;                   // Entry # of node in the node vector.
     unsigned NodeQueueId;               // Queue id of node.
     unsigned short Latency;             // Node latency.
-    short NumPreds;                     // # of preds.
-    short NumSuccs;                     // # of sucss.
+    short NumPreds;                     // # of non-control preds.
+    short NumSuccs;                     // # of non-control sucss.
     short NumPredsLeft;                 // # of preds not scheduled.
     short NumSuccsLeft;                 // # of succs not scheduled.
     bool isTwoAddress     : 1;          // Is a two-address instruction.
@@ -127,14 +129,54 @@ namespace llvm {
     const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
     const TargetRegisterClass *CopySrcRC;
     
+    /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
+    /// an SDNode and any nodes flagged to it.
     SUnit(SDNode *node, unsigned nodenum)
-      : Node(node), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0),
-        NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
+      : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
+        Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
+        isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+        isPending(false), isAvailable(false), isScheduled(false),
+        CycleBound(0), Cycle(0), Depth(0), Height(0),
+        CopyDstRC(NULL), CopySrcRC(NULL) {}
+
+    /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
+    /// a MachineInstr.
+    SUnit(MachineInstr *instr, unsigned nodenum)
+      : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
+        Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
         isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
         isPending(false), isAvailable(false), isScheduled(false),
         CycleBound(0), Cycle(0), Depth(0), Height(0),
         CopyDstRC(NULL), CopySrcRC(NULL) {}
 
+    /// setNode - Assign the representative SDNode for this SUnit.
+    /// This may be used during pre-regalloc scheduling.
+    void setNode(SDNode *N) {
+      assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
+      Node = N;
+    }
+
+    /// getNode - Return the representative SDNode for this SUnit.
+    /// This may be used during pre-regalloc scheduling.
+    SDNode *getNode() const {
+      assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
+      return Node;
+    }
+
+    /// setInstr - Assign the instruction for the SUnit.
+    /// This may be used during post-regalloc scheduling.
+    void setInstr(MachineInstr *MI) {
+      assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
+      Instr = MI;
+    }
+
+    /// getInstr - Return the representative MachineInstr for this SUnit.
+    /// This may be used during post-regalloc scheduling.
+    MachineInstr *getInstr() const {
+      assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
+      return Instr;
+    }
+
     /// addPred - This adds the specified node as a pred of the current node if
     /// not already.  This returns true if this is a new pred.
     bool addPred(SUnit *N, bool isCtrl, bool isSpecial,
@@ -239,7 +281,7 @@ namespace llvm {
 
   class ScheduleDAG {
   public:
-    SelectionDAG &DAG;                    // DAG of the current basic block
+    SelectionDAG *DAG;                    // DAG of the current basic block
     MachineBasicBlock *BB;                // Current basic block
     const TargetMachine &TM;              // Target processor
     const TargetInstrInfo *TII;           // Target instruction information
@@ -253,7 +295,7 @@ namespace llvm {
     std::vector<SUnit> SUnits;            // The scheduling units.
     SmallSet<SDNode*, 16> CommuteSet;     // Nodes that should be commuted.
 
-    ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
+    ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
                 const TargetMachine &tm);
 
     virtual ~ScheduleDAG() {}
@@ -278,7 +320,7 @@ namespace llvm {
       if (isa<FrameIndexSDNode>(Node))     return true;
       if (isa<ConstantPoolSDNode>(Node))   return true;
       if (isa<JumpTableSDNode>(Node))      return true;
-      if (isa<SymbolSDNode>(Node))         return true;
+      if (isa<ExternalSymbolSDNode>(Node)) return true;
       if (isa<MemOperandSDNode>(Node))     return true;
       if (Node->getOpcode() == ISD::EntryToken) return true;
       return false;
@@ -362,7 +404,6 @@ namespace llvm {
     void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
                     const TargetInstrDesc *II,
                     DenseMap<SDValue, unsigned> &VRBaseMap);
-
     void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
 
     void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
@@ -396,6 +437,7 @@ namespace llvm {
   /// reduction list scheduler.
   ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
                                           SelectionDAG *DAG,
+                                          const TargetMachine *TM,
                                           MachineBasicBlock *BB,
                                           bool Fast);
   
@@ -403,6 +445,7 @@ namespace llvm {
   /// reduction list scheduler.
   ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
                                           SelectionDAG *DAG,
+                                          const TargetMachine *TM,
                                           MachineBasicBlock *BB,
                                           bool Fast);
   
@@ -410,13 +453,23 @@ namespace llvm {
   /// a hazard recognizer.
   ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
                                         SelectionDAG *DAG,
+                                        const TargetMachine *TM,
                                         MachineBasicBlock *BB,
                                         bool Fast);
                                         
+  /// createFastDAGScheduler - This creates a "fast" scheduler.
+  ///
+  ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
+                                      SelectionDAG *DAG,
+                                      const TargetMachine *TM,
+                                      MachineBasicBlock *BB,
+                                      bool Fast);
+
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
   /// for the target.
   ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
                                       SelectionDAG *DAG,
+                                      const TargetMachine *TM,
                                       MachineBasicBlock *BB,
                                       bool Fast);