//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Evan Cheng and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the ScheduleDAG class, which is used as the common
-// base class for SelectionDAG-based instruction scheduler.
+// base class for instruction schedulers.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_SCHEDULEDAG_H
#define LLVM_CODEGEN_SCHEDULEDAG_H
-#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/GraphTraits.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/PointerIntPair.h"
namespace llvm {
- struct InstrStage;
+ class SUnit;
class MachineConstantPool;
- class MachineDebugInfo;
+ class MachineFunction;
+ class MachineModuleInfo;
+ class MachineRegisterInfo;
class MachineInstr;
- class MRegisterInfo;
- class SelectionDAG;
- class SSARegMap;
+ class TargetRegisterInfo;
+ class ScheduleDAG;
+ class SDNode;
class TargetInstrInfo;
- class TargetInstrDescriptor;
+ class TargetInstrDesc;
+ class TargetLowering;
class TargetMachine;
+ class TargetRegisterClass;
+ template<class Graph> class GraphWriter;
- class NodeInfo;
- typedef NodeInfo *NodeInfoPtr;
- typedef std::vector<NodeInfoPtr> NIVector;
- typedef std::vector<NodeInfoPtr>::iterator NIIterator;
-
- // Scheduling heuristics
- enum SchedHeuristics {
- defaultScheduling, // Let the target specify its preference.
- noScheduling, // No scheduling, emit breadth first sequence.
- simpleScheduling, // Two pass, min. critical path, max. utilization.
- simpleNoItinScheduling, // Same as above exact using generic latency.
- listSchedulingBURR, // Bottom up reg reduction list scheduling.
- listSchedulingTD // Top-down list scheduler.
- };
-
- /// HazardRecognizer - This determines whether or not an instruction can be
- /// issued this cycle, and whether or not a noop needs to be inserted to handle
- /// the hazard.
- class HazardRecognizer {
+ /// SDep - Scheduling dependency. This represents one direction of an
+ /// edge in the scheduling DAG.
+ class SDep {
public:
- virtual ~HazardRecognizer();
-
- enum HazardType {
- NoHazard, // This instruction can be emitted at this cycle.
- Hazard, // This instruction can't be emitted at this cycle.
- NoopHazard, // This instruction can't be emitted, and needs noops.
+ /// Kind - These are the different kinds of scheduling dependencies.
+ enum Kind {
+ Data, ///< Regular data dependence (aka true-dependence).
+ Anti, ///< A register anti-dependedence (aka WAR).
+ Output, ///< A register output-dependence (aka WAW).
+ Order ///< Any other ordering dependency.
};
-
- /// getHazardType - Return the hazard type of emitting this node. There are
- /// three possible results. Either:
- /// * NoHazard: it is legal to issue this instruction on this cycle.
- /// * Hazard: issuing this instruction would stall the machine. If some
- /// other instruction is available, issue it first.
- /// * NoopHazard: issuing this instruction would break the program. If
- /// some other instruction can be issued, do so, otherwise issue a noop.
- virtual HazardType getHazardType(SDNode *Node) {
- return NoHazard;
+
+ private:
+ /// Dep - A pointer to the depending/depended-on SUnit, and an enum
+ /// indicating the kind of the dependency.
+ PointerIntPair<SUnit *, 2, Kind> Dep;
+
+ /// Contents - A union discriminated by the dependence kind.
+ union {
+ /// Reg - For Data, Anti, and Output dependencies, the associated
+ /// register. For Data dependencies that don't currently have a register
+ /// assigned, this is set to zero.
+ unsigned Reg;
+
+ /// Order - Additional information about Order dependencies.
+ struct {
+ /// isNormalMemory - True if both sides of the dependence
+ /// access memory in non-volatile and fully modeled ways.
+ bool isNormalMemory : 1;
+
+ /// isMustAlias - True if both sides of the dependence are known to
+ /// access the same memory.
+ bool isMustAlias : 1;
+
+ /// isArtificial - True if this is an artificial dependency, meaning
+ /// it is not necessary for program correctness, and may be safely
+ /// deleted if necessary.
+ bool isArtificial : 1;
+ } Order;
+ } Contents;
+
+ /// Latency - The time associated with this edge. Often this is just
+ /// the value of the Latency field of the predecessor, however advanced
+ /// models may provide additional information about specific edges.
+ unsigned Latency;
+
+ public:
+ /// SDep - Construct a null SDep. This is only for use by container
+ /// classes which require default constructors. SUnits may not
+ /// have null SDep edges.
+ SDep() : Dep(0, Data) {}
+
+ /// SDep - Construct an SDep with the specified values.
+ SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
+ bool isNormalMemory = false, bool isMustAlias = false,
+ bool isArtificial = false)
+ : Dep(S, kind), Contents(), Latency(latency) {
+ switch (kind) {
+ case Anti:
+ case Output:
+ assert(Reg != 0 &&
+ "SDep::Anti and SDep::Output must use a non-zero Reg!");
+ // fall through
+ case Data:
+ assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
+ assert(!isArtificial && "isArtificial only applies with SDep::Order!");
+ Contents.Reg = Reg;
+ break;
+ case Order:
+ assert(Reg == 0 && "Reg given for non-register dependence!");
+ Contents.Order.isNormalMemory = isNormalMemory;
+ Contents.Order.isMustAlias = isMustAlias;
+ Contents.Order.isArtificial = isArtificial;
+ break;
+ }
}
-
- /// EmitInstruction - This callback is invoked when an instruction is
- /// emitted, to advance the hazard state.
- virtual void EmitInstruction(SDNode *Node) {
+
+ bool operator==(const SDep &Other) const {
+ if (Dep != Other.Dep || Latency != Other.Latency) return false;
+ switch (Dep.getInt()) {
+ case Data:
+ case Anti:
+ case Output:
+ return Contents.Reg == Other.Contents.Reg;
+ case Order:
+ return Contents.Order.isNormalMemory ==
+ Other.Contents.Order.isNormalMemory &&
+ Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
+ Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
+ }
+ assert(0 && "Invalid dependency kind!");
+ return false;
}
-
- /// AdvanceCycle - This callback is invoked when no instructions can be
- /// issued on this cycle without a hazard. This should increment the
- /// internal state of the hazard recognizer so that previously "Hazard"
- /// instructions will now not be hazards.
- virtual void AdvanceCycle() {
+
+ bool operator!=(const SDep &Other) const {
+ return !operator==(Other);
}
-
- /// EmitNoop - This callback is invoked when a noop was added to the
- /// instruction stream.
- virtual void EmitNoop() {
+
+ /// getLatency - Return the latency value for this edge, which roughly
+ /// means the minimum number of cycles that must elapse between the
+ /// predecessor and the successor, given that they have this edge
+ /// between them.
+ unsigned getLatency() const {
+ return Latency;
}
- };
- //===--------------------------------------------------------------------===//
- ///
- /// Node group - This struct is used to manage flagged node groups.
- ///
- class NodeGroup {
- public:
- NodeGroup *Next;
- private:
- NIVector Members; // Group member nodes
- NodeInfo *Dominator; // Node with highest latency
- unsigned Latency; // Total latency of the group
- int Pending; // Number of visits pending before
- // adding to order
+ //// getSUnit - Return the SUnit to which this edge points.
+ SUnit *getSUnit() const {
+ return Dep.getPointer();
+ }
- public:
- // Ctor.
- NodeGroup() : Next(NULL), Dominator(NULL), Pending(0) {}
-
- // Accessors
- inline void setDominator(NodeInfo *D) { Dominator = D; }
- inline NodeInfo *getTop() { return Members.front(); }
- inline NodeInfo *getBottom() { return Members.back(); }
- inline NodeInfo *getDominator() { return Dominator; }
- inline void setLatency(unsigned L) { Latency = L; }
- inline unsigned getLatency() { return Latency; }
- inline int getPending() const { return Pending; }
- inline void setPending(int P) { Pending = P; }
- inline int addPending(int I) { return Pending += I; }
-
- // Pass thru
- inline bool group_empty() { return Members.empty(); }
- inline NIIterator group_begin() { return Members.begin(); }
- inline NIIterator group_end() { return Members.end(); }
- inline void group_push_back(const NodeInfoPtr &NI) {
- Members.push_back(NI);
+ //// setSUnit - Assign the SUnit to which this edge points.
+ void setSUnit(SUnit *SU) {
+ Dep.setPointer(SU);
}
- inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
- return Members.insert(Pos, NI);
+
+ /// getKind - Return an enum value representing the kind of the dependence.
+ Kind getKind() const {
+ return Dep.getInt();
+ }
+
+ /// isCtrl - Shorthand for getKind() != SDep::Data.
+ bool isCtrl() const {
+ return getKind() != Data;
}
- inline void group_insert(NIIterator Pos, NIIterator First,
- NIIterator Last) {
- Members.insert(Pos, First, Last);
+
+ /// isNormalMemory - Test if this is an Order dependence between two
+ /// memory accesses where both sides of the dependence access memory
+ /// in non-volatile and fully modeled ways.
+ bool isNormalMemory() const {
+ return getKind() == Order && Contents.Order.isNormalMemory;
+ }
+
+ /// isMustAlias - Test if this is an Order dependence that is marked
+ /// as "must alias", meaning that the SUnits at either end of the edge
+ /// have a memory dependence on a known memory location.
+ bool isMustAlias() const {
+ return getKind() == Order && Contents.Order.isMustAlias;
}
- static void Add(NodeInfo *D, NodeInfo *U);
+ /// isArtificial - Test if this is an Order dependence that is marked
+ /// as "artificial", meaning it isn't necessary for correctness.
+ bool isArtificial() const {
+ return getKind() == Order && Contents.Order.isArtificial;
+ }
+
+ /// isAssignedRegDep - Test if this is a Data dependence that is
+ /// associated with a register.
+ bool isAssignedRegDep() const {
+ return getKind() == Data && Contents.Reg != 0;
+ }
+
+ /// getReg - Return the register associated with this edge. This is
+ /// only valid on Data, Anti, and Output edges. On Data edges, this
+ /// value may be zero, meaning there is no associated register.
+ unsigned getReg() const {
+ assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
+ "getReg called on non-register dependence edge!");
+ return Contents.Reg;
+ }
+
+ /// setReg - Assign the associated register for this edge. This is
+ /// only valid on Data, Anti, and Output edges. On Anti and Output
+ /// edges, this value must not be zero. On Data edges, the value may
+ /// be zero, which would mean that no specific register is associated
+ /// with this edge.
+ void setReg(unsigned Reg) {
+ assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
+ "setReg called on non-register dependence edge!");
+ assert((getKind() != Anti || Reg != 0) &&
+ "SDep::Anti edge cannot use the zero register!");
+ assert((getKind() != Output || Reg != 0) &&
+ "SDep::Output edge cannot use the zero register!");
+ Contents.Reg = Reg;
+ }
};
- //===--------------------------------------------------------------------===//
- ///
- /// NodeInfo - This struct tracks information used to schedule the a node.
- ///
- class NodeInfo {
+ /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
+ class SUnit {
private:
- int Pending; // Number of visits pending before
- // adding to order
+ SDNode *Node; // Representative node.
+ MachineInstr *Instr; // Alternatively, a MachineInstr.
public:
- SDNode *Node; // DAG node
- InstrStage *StageBegin; // First stage in itinerary
- InstrStage *StageEnd; // Last+1 stage in itinerary
- unsigned Latency; // Total cycles to complete instr
- bool IsCall : 1; // Is function call
- bool IsLoad : 1; // Is memory load
- bool IsStore : 1; // Is memory store
- unsigned Slot; // Node's time slot
- NodeGroup *Group; // Grouping information
-#ifndef NDEBUG
- unsigned Preorder; // Index before scheduling
-#endif
+ SUnit *OrigNode; // If not this, the node from which
+ // this node was cloned.
+
+ // Preds/Succs - The SUnits before/after us in the graph. The boolean value
+ // is true if the edge is a token chain edge, false if it is a value edge.
+ SmallVector<SDep, 4> Preds; // All sunit predecessors.
+ SmallVector<SDep, 4> Succs; // All sunit successors.
- // Ctor.
- NodeInfo(SDNode *N = NULL)
- : Pending(0)
- , Node(N)
- , StageBegin(NULL)
- , StageEnd(NULL)
- , Latency(0)
- , IsCall(false)
- , Slot(0)
- , Group(NULL)
-#ifndef NDEBUG
- , Preorder(0)
-#endif
- {}
-
- // Accessors
- inline bool isInGroup() const {
- assert(!Group || !Group->group_empty() && "Group with no members");
- return Group != NULL;
+ typedef SmallVector<SDep, 4>::iterator pred_iterator;
+ typedef SmallVector<SDep, 4>::iterator succ_iterator;
+ typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
+ typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
+
+ unsigned NodeNum; // Entry # of node in the node vector.
+ unsigned NodeQueueId; // Queue id of node.
+ unsigned short Latency; // Node latency.
+ short NumPreds; // # of SDep::Data preds.
+ short NumSuccs; // # of SDep::Data sucss.
+ short NumPredsLeft; // # of preds not scheduled.
+ short NumSuccsLeft; // # of succs not scheduled.
+ bool isTwoAddress : 1; // Is a two-address instruction.
+ bool isCommutable : 1; // Is a commutable instruction.
+ bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
+ bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
+ bool isPending : 1; // True once pending.
+ bool isAvailable : 1; // True once available.
+ bool isScheduled : 1; // True once scheduled.
+ bool isScheduleHigh : 1; // True if preferable to schedule high.
+ bool isCloned : 1; // True if this node has been cloned.
+ private:
+ bool isDepthCurrent : 1; // True if Depth is current.
+ bool isHeightCurrent : 1; // True if Height is current.
+ unsigned Depth; // Node depth.
+ unsigned Height; // Node height.
+ public:
+ const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
+ const TargetRegisterClass *CopySrcRC;
+
+ /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
+ /// an SDNode and any nodes flagged to it.
+ SUnit(SDNode *node, unsigned nodenum)
+ : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
+ Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
+ isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+ hasPhysRegClobbers(false),
+ isPending(false), isAvailable(false), isScheduled(false),
+ isScheduleHigh(false), isCloned(false),
+ isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
+ CopyDstRC(NULL), CopySrcRC(NULL) {}
+
+ /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
+ /// a MachineInstr.
+ SUnit(MachineInstr *instr, unsigned nodenum)
+ : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
+ Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
+ isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+ hasPhysRegClobbers(false),
+ isPending(false), isAvailable(false), isScheduled(false),
+ isScheduleHigh(false), isCloned(false),
+ isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
+ CopyDstRC(NULL), CopySrcRC(NULL) {}
+
+ /// SUnit - Construct a placeholder SUnit.
+ SUnit()
+ : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0),
+ Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
+ isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+ hasPhysRegClobbers(false),
+ isPending(false), isAvailable(false), isScheduled(false),
+ isScheduleHigh(false), isCloned(false),
+ isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
+ CopyDstRC(NULL), CopySrcRC(NULL) {}
+
+ /// setNode - Assign the representative SDNode for this SUnit.
+ /// This may be used during pre-regalloc scheduling.
+ void setNode(SDNode *N) {
+ assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
+ Node = N;
}
- inline bool isGroupDominator() const {
- return isInGroup() && Group->getDominator() == this;
+
+ /// getNode - Return the representative SDNode for this SUnit.
+ /// This may be used during pre-regalloc scheduling.
+ SDNode *getNode() const {
+ assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
+ return Node;
}
- inline int getPending() const {
- return Group ? Group->getPending() : Pending;
+
+ /// setInstr - Assign the instruction for the SUnit.
+ /// This may be used during post-regalloc scheduling.
+ void setInstr(MachineInstr *MI) {
+ assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
+ Instr = MI;
}
- inline void setPending(int P) {
- if (Group) Group->setPending(P);
- else Pending = P;
+
+ /// getInstr - Return the representative MachineInstr for this SUnit.
+ /// This may be used during post-regalloc scheduling.
+ MachineInstr *getInstr() const {
+ assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
+ return Instr;
}
- inline int addPending(int I) {
- if (Group) return Group->addPending(I);
- else return Pending += I;
+
+ /// addPred - This adds the specified edge as a pred of the current node if
+ /// not already. It also adds the current node as a successor of the
+ /// specified node.
+ void addPred(const SDep &D);
+
+ /// removePred - This removes the specified edge as a pred of the current
+ /// node if it exists. It also removes the current node as a successor of
+ /// the specified node.
+ void removePred(const SDep &D);
+
+ /// getDepth - Return the depth of this node, which is the length of the
+ /// maximum path up to any node with has no predecessors.
+ unsigned getDepth() const {
+ if (!isDepthCurrent) const_cast<SUnit *>(this)->ComputeDepth();
+ return Depth;
}
- };
- //===--------------------------------------------------------------------===//
- ///
- /// NodeGroupIterator - Iterates over all the nodes indicated by the node
- /// info. If the node is in a group then iterate over the members of the
- /// group, otherwise just the node info.
- ///
- class NodeGroupIterator {
- private:
- NodeInfo *NI; // Node info
- NIIterator NGI; // Node group iterator
- NIIterator NGE; // Node group iterator end
-
- public:
- // Ctor.
- NodeGroupIterator(NodeInfo *N) : NI(N) {
- // If the node is in a group then set up the group iterator. Otherwise
- // the group iterators will trip first time out.
- if (N->isInGroup()) {
- // get Group
- NodeGroup *Group = NI->Group;
- NGI = Group->group_begin();
- NGE = Group->group_end();
- // Prevent this node from being used (will be in members list
- NI = NULL;
- }
+ /// getHeight - Return the height of this node, which is the length of the
+ /// maximum path down to any node with has no successors.
+ unsigned getHeight() const {
+ if (!isHeightCurrent) const_cast<SUnit *>(this)->ComputeHeight();
+ return Height;
}
-
- /// next - Return the next node info, otherwise NULL.
- ///
- NodeInfo *next() {
- // If members list
- if (NGI != NGE) return *NGI++;
- // Use node as the result (may be NULL)
- NodeInfo *Result = NI;
- // Only use once
- NI = NULL;
- // Return node or NULL
- return Result;
+
+ /// setDepthToAtLeast - If NewDepth is greater than this node's depth
+ /// value, set it to be the new depth value. This also recursively
+ /// marks successor nodes dirty.
+ void setDepthToAtLeast(unsigned NewDepth);
+
+ /// setDepthToAtLeast - If NewDepth is greater than this node's depth
+ /// value, set it to be the new height value. This also recursively
+ /// marks predecessor nodes dirty.
+ void setHeightToAtLeast(unsigned NewHeight);
+
+ /// setDepthDirty - Set a flag in this node to indicate that its
+ /// stored Depth value will require recomputation the next time
+ /// getDepth() is called.
+ void setDepthDirty();
+
+ /// setHeightDirty - Set a flag in this node to indicate that its
+ /// stored Height value will require recomputation the next time
+ /// getHeight() is called.
+ void setHeightDirty();
+
+ /// isPred - Test if node N is a predecessor of this node.
+ bool isPred(SUnit *N) {
+ for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
+ if (Preds[i].getSUnit() == N)
+ return true;
+ return false;
}
- };
- //===--------------------------------------------------------------------===//
+
+ /// isSucc - Test if node N is a successor of this node.
+ bool isSucc(SUnit *N) {
+ for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
+ if (Succs[i].getSUnit() == N)
+ return true;
+ return false;
+ }
+
+ void dump(const ScheduleDAG *G) const;
+ void dumpAll(const ScheduleDAG *G) const;
+ void print(raw_ostream &O, const ScheduleDAG *G) const;
+ private:
+ void ComputeDepth();
+ void ComputeHeight();
+ };
//===--------------------------------------------------------------------===//
- ///
- /// NodeGroupOpIterator - Iterates over all the operands of a node. If the
- /// node is a member of a group, this iterates over all the operands of all
- /// the members of the group.
- ///
- class NodeGroupOpIterator {
- private:
- NodeInfo *NI; // Node containing operands
- NodeGroupIterator GI; // Node group iterator
- SDNode::op_iterator OI; // Operand iterator
- SDNode::op_iterator OE; // Operand iterator end
-
- /// CheckNode - Test if node has more operands. If not get the next node
- /// skipping over nodes that have no operands.
- void CheckNode() {
- // Only if operands are exhausted first
- while (OI == OE) {
- // Get next node info
- NodeInfo *NI = GI.next();
- // Exit if nodes are exhausted
- if (!NI) return;
- // Get node itself
- SDNode *Node = NI->Node;
- // Set up the operand iterators
- OI = Node->op_begin();
- OE = Node->op_end();
- }
- }
-
+ /// SchedulingPriorityQueue - This interface is used to plug different
+ /// priorities computation algorithms into the list scheduler. It implements
+ /// the interface of a standard priority queue, where nodes are inserted in
+ /// arbitrary order and returned in priority order. The computation of the
+ /// priority and the representation of the queue are totally up to the
+ /// implementation to decide.
+ ///
+ class SchedulingPriorityQueue {
public:
- // Ctor.
- NodeGroupOpIterator(NodeInfo *N)
- : NI(N), GI(N), OI(SDNode::op_iterator()), OE(SDNode::op_iterator()) {}
+ virtual ~SchedulingPriorityQueue() {}
- /// isEnd - Returns true when not more operands are available.
- ///
- inline bool isEnd() { CheckNode(); return OI == OE; }
+ virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
+ virtual void addNode(const SUnit *SU) = 0;
+ virtual void updateNode(const SUnit *SU) = 0;
+ virtual void releaseState() = 0;
+
+ virtual unsigned size() const = 0;
+ virtual bool empty() const = 0;
+ virtual void push(SUnit *U) = 0;
- /// next - Returns the next available operand.
+ virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
+ virtual SUnit *pop() = 0;
+
+ virtual void remove(SUnit *SU) = 0;
+
+ /// ScheduledNode - As each node is scheduled, this method is invoked. This
+ /// allows the priority function to adjust the priority of related
+ /// unscheduled nodes, for example.
///
- inline SDOperand next() {
- assert(OI != OE &&
- "Not checking for end of NodeGroupOpIterator correctly");
- return *OI++;
- }
+ virtual void ScheduledNode(SUnit *) {}
+
+ virtual void UnscheduledNode(SUnit *) {}
};
class ScheduleDAG {
public:
- SchedHeuristics Heuristic; // Scheduling heuristic
- SelectionDAG &DAG; // DAG of the current basic block
- MachineBasicBlock *BB; // Current basic block
+ MachineBasicBlock *BB; // The block in which to insert instructions.
+ MachineBasicBlock::iterator InsertPos;// The position to insert instructions.
const TargetMachine &TM; // Target processor
const TargetInstrInfo *TII; // Target instruction information
- const MRegisterInfo *MRI; // Target processor register info
- SSARegMap *RegMap; // Virtual/real register map
+ const TargetRegisterInfo *TRI; // Target processor register info
+ const TargetLowering *TLI; // Target lowering info
+ MachineFunction &MF; // Machine function
+ MachineRegisterInfo &MRI; // Virtual/real register map
MachineConstantPool *ConstPool; // Target constant pool
- std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
- unsigned NodeCount; // Number of nodes in DAG
- bool HasGroups; // True if there are any groups
- NodeInfo *Info; // Info for nodes being scheduled
- NIVector Ordering; // Emit ordering of nodes
- NodeGroup *HeadNG, *TailNG; // Keep track of allocated NodeGroups
-
- ScheduleDAG(SchedHeuristics hstc, SelectionDAG &dag, MachineBasicBlock *bb,
- const TargetMachine &tm)
- : Heuristic(hstc), DAG(dag), BB(bb), TM(tm), NodeCount(0),
- HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {}
-
- virtual ~ScheduleDAG() {
- if (Info)
- delete[] Info;
-
- NodeGroup *NG = HeadNG;
- while (NG) {
- NodeGroup *NextSU = NG->Next;
- delete NG;
- NG = NextSU;
- }
- };
+ std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
+ // represent noop instructions.
+ std::vector<SUnit> SUnits; // The scheduling units.
+ SUnit EntrySU; // Special node for the region entry.
+ SUnit ExitSU; // Special node for the region exit.
- /// Run - perform scheduling.
- ///
- MachineBasicBlock *Run();
+ explicit ScheduleDAG(MachineFunction &mf);
- /// getNI - Returns the node info for the specified node.
+ virtual ~ScheduleDAG();
+
+ /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
+ /// using 'dot'.
///
- NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
+ void viewGraph();
- /// isPassiveNode - Return true if the node is a non-scheduled leaf.
+ /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
+ /// according to the order specified in Sequence.
///
- static bool isPassiveNode(SDNode *Node) {
- if (isa<ConstantSDNode>(Node)) return true;
- if (isa<RegisterSDNode>(Node)) return true;
- if (isa<GlobalAddressSDNode>(Node)) return true;
- if (isa<BasicBlockSDNode>(Node)) return true;
- if (isa<FrameIndexSDNode>(Node)) return true;
- if (isa<ConstantPoolSDNode>(Node)) return true;
- if (isa<ExternalSymbolSDNode>(Node)) return true;
- return false;
- }
+ virtual MachineBasicBlock *EmitSchedule() = 0;
- /// EmitNode - Generate machine code for an node and needed dependencies.
- /// VRBaseMap contains, for each already emitted node, the first virtual
- /// register number for the results of the node.
- ///
- void EmitNode(SDNode *Node, std::map<SDNode*, unsigned> &VRBaseMap);
-
- /// EmitNoop - Emit a noop instruction.
- ///
- void EmitNoop();
-
- /// EmitAll - Emit all nodes in schedule sorted order.
+ void dumpSchedule() const;
+
+ virtual void dumpNode(const SUnit *SU) const = 0;
+
+ /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
+ /// of the ScheduleDAG.
+ virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
+
+ /// addCustomGraphFeatures - Add custom features for a visualization of
+ /// the ScheduleDAG.
+ virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
+
+#ifndef NDEBUG
+ /// VerifySchedule - Verify that all SUnits were scheduled and that
+ /// their state is consistent.
+ void VerifySchedule(bool isBottomUp);
+#endif
+
+ protected:
+ /// Run - perform scheduling.
///
- void EmitAll();
+ void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
- /// Schedule - Order nodes according to selected style.
+ /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
+ /// to form the scheduling dependency graph.
///
- virtual void Schedule() {}
+ virtual void BuildSchedGraph() = 0;
- /// printNI - Print node info.
+ /// ComputeLatency - Compute node latency.
///
- void printNI(std::ostream &O, NodeInfo *NI) const;
+ virtual void ComputeLatency(SUnit *SU) = 0;
- /// printChanges - Hilight changes in order caused by scheduling.
+ /// Schedule - Order nodes according to selected style, filling
+ /// in the Sequence member.
///
- void printChanges(unsigned Index) const;
+ virtual void Schedule() = 0;
- /// print - Print ordering to specified output stream.
+ /// ForceUnitLatencies - Return true if all scheduling edges should be given a
+ /// latency value of one. The default is to return false; schedulers may
+ /// override this as needed.
+ virtual bool ForceUnitLatencies() const { return false; }
+
+ /// EmitNoop - Emit a noop instruction.
///
- void print(std::ostream &O) const;
+ void EmitNoop();
- void dump(const char *tag) const;
+ void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
- virtual void dump() const;
+ void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
private:
- void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
- const TargetInstrDescriptor *II,
- std::map<SDNode*, unsigned> &VRBaseMap);
-
- void AddToGroup(NodeInfo *D, NodeInfo *U);
-protected:
- /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
- ///
- void PrepareNodeInfo();
-
- /// IdentifyGroups - Put flagged nodes into groups.
- ///
- void IdentifyGroups();
+ /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
+ /// physical register has only a single copy use, then coalesced the copy
+ /// if possible.
+ void EmitLiveInCopy(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator &InsertPos,
+ unsigned VirtReg, unsigned PhysReg,
+ const TargetRegisterClass *RC,
+ DenseMap<MachineInstr*, unsigned> &CopyRegMap);
+
+ /// EmitLiveInCopies - If this is the first basic block in the function,
+ /// and if it has live ins that need to be copied into vregs, emit the
+ /// copies into the top of the block.
+ void EmitLiveInCopies(MachineBasicBlock *MBB);
};
- /// createSimpleDAGScheduler - This creates a simple two pass instruction
- /// scheduler.
- ScheduleDAG* createSimpleDAGScheduler(SchedHeuristics Heuristic,
- SelectionDAG &DAG,
- MachineBasicBlock *BB);
+ class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> {
+ SUnit *Node;
+ unsigned Operand;
- /// createBURRListDAGScheduler - This creates a bottom up register usage
- /// reduction list scheduler.
- ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
- MachineBasicBlock *BB);
-
- /// createTDListDAGScheduler - This creates a top-down list scheduler with
- /// the specified hazard recognizer. This takes ownership of the hazard
- /// recognizer and deletes it when done.
- ScheduleDAG* createTDListDAGScheduler(SelectionDAG &DAG,
- MachineBasicBlock *BB,
- HazardRecognizer *HR);
+ SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
+ public:
+ bool operator==(const SUnitIterator& x) const {
+ return Operand == x.Operand;
+ }
+ bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
+
+ const SUnitIterator &operator=(const SUnitIterator &I) {
+ assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
+ Operand = I.Operand;
+ return *this;
+ }
+
+ pointer operator*() const {
+ return Node->Preds[Operand].getSUnit();
+ }
+ pointer operator->() const { return operator*(); }
+
+ SUnitIterator& operator++() { // Preincrement
+ ++Operand;
+ return *this;
+ }
+ SUnitIterator operator++(int) { // Postincrement
+ SUnitIterator tmp = *this; ++*this; return tmp;
+ }
+
+ static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
+ static SUnitIterator end (SUnit *N) {
+ return SUnitIterator(N, (unsigned)N->Preds.size());
+ }
+
+ unsigned getOperand() const { return Operand; }
+ const SUnit *getNode() const { return Node; }
+ /// isCtrlDep - Test if this is not an SDep::Data dependence.
+ bool isCtrlDep() const {
+ return getSDep().isCtrl();
+ }
+ bool isArtificialDep() const {
+ return getSDep().isArtificial();
+ }
+ const SDep &getSDep() const {
+ return Node->Preds[Operand];
+ }
+ };
+
+ template <> struct GraphTraits<SUnit*> {
+ typedef SUnit NodeType;
+ typedef SUnitIterator ChildIteratorType;
+ static inline NodeType *getEntryNode(SUnit *N) { return N; }
+ static inline ChildIteratorType child_begin(NodeType *N) {
+ return SUnitIterator::begin(N);
+ }
+ static inline ChildIteratorType child_end(NodeType *N) {
+ return SUnitIterator::end(N);
+ }
+ };
+
+ template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
+ typedef std::vector<SUnit>::iterator nodes_iterator;
+ static nodes_iterator nodes_begin(ScheduleDAG *G) {
+ return G->SUnits.begin();
+ }
+ static nodes_iterator nodes_end(ScheduleDAG *G) {
+ return G->SUnits.end();
+ }
+ };
+
+ /// ScheduleDAGTopologicalSort is a class that computes a topological
+ /// ordering for SUnits and provides methods for dynamically updating
+ /// the ordering as new edges are added.
+ ///
+ /// This allows a very fast implementation of IsReachable, for example.
+ ///
+ class ScheduleDAGTopologicalSort {
+ /// SUnits - A reference to the ScheduleDAG's SUnits.
+ std::vector<SUnit> &SUnits;
+
+ /// Index2Node - Maps topological index to the node number.
+ std::vector<int> Index2Node;
+ /// Node2Index - Maps the node number to its topological index.
+ std::vector<int> Node2Index;
+ /// Visited - a set of nodes visited during a DFS traversal.
+ BitVector Visited;
+
+ /// DFS - make a DFS traversal and mark all nodes affected by the
+ /// edge insertion. These nodes will later get new topological indexes
+ /// by means of the Shift method.
+ void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
+
+ /// Shift - reassign topological indexes for the nodes in the DAG
+ /// to preserve the topological ordering.
+ void Shift(BitVector& Visited, int LowerBound, int UpperBound);
+
+ /// Allocate - assign the topological index to the node n.
+ void Allocate(int n, int index);
+
+ public:
+ explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
+
+ /// InitDAGTopologicalSorting - create the initial topological
+ /// ordering from the DAG to be scheduled.
+ void InitDAGTopologicalSorting();
+
+ /// IsReachable - Checks if SU is reachable from TargetSU.
+ bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
+
+ /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
+ /// will create a cycle.
+ bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
+
+ /// AddPred - Updates the topological ordering to accomodate an edge
+ /// to be added from SUnit X to SUnit Y.
+ void AddPred(SUnit *Y, SUnit *X);
+
+ /// RemovePred - Updates the topological ordering to accomodate an
+ /// an edge to be removed from the specified node N from the predecessors
+ /// of the current node M.
+ void RemovePred(SUnit *M, SUnit *N);
+
+ typedef std::vector<int>::iterator iterator;
+ typedef std::vector<int>::const_iterator const_iterator;
+ iterator begin() { return Index2Node.begin(); }
+ const_iterator begin() const { return Index2Node.begin(); }
+ iterator end() { return Index2Node.end(); }
+ const_iterator end() const { return Index2Node.end(); }
+
+ typedef std::vector<int>::reverse_iterator reverse_iterator;
+ typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
+ reverse_iterator rbegin() { return Index2Node.rbegin(); }
+ const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
+ reverse_iterator rend() { return Index2Node.rend(); }
+ const_reverse_iterator rend() const { return Index2Node.rend(); }
+ };
}
#endif
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