no really, I can spell!

[oota-llvm.git] / include / llvm / CodeGen / ScheduleDAG.h

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index c62c3af232f9f4c17a408dea2007ac806ea2599a..237d491e8262238664dc7f19f2aed68ff16f5230 100644 (file)
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -23,7 +23,7 @@
 #include "llvm/ADT/PointerIntPair.h"
 
 namespace llvm {
-  struct SUnit;
+  class SUnit;
   class MachineConstantPool;
   class MachineFunction;
   class MachineModuleInfo;
@@ -31,7 +31,6 @@ namespace llvm {
   class MachineInstr;
   class TargetRegisterInfo;
   class ScheduleDAG;
-  class SelectionDAG;
   class SDNode;
   class TargetInstrInfo;
   class TargetInstrDesc;
@@ -218,7 +217,7 @@ namespace llvm {
   };
 
   /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
-  struct SUnit {
+  class SUnit {
   private:
     SDNode *Node;                       // Representative node.
     MachineInstr *Instr;                // Alternatively, a MachineInstr.
@@ -246,6 +245,7 @@ namespace llvm {
     bool isTwoAddress     : 1;          // Is a two-address instruction.
     bool isCommutable     : 1;          // Is a commutable instruction.
     bool hasPhysRegDefs   : 1;          // Has physreg defs that are being used.
+    bool hasPhysRegClobbers : 1;        // Has any physreg defs, used or not.
     bool isPending        : 1;          // True once pending.
     bool isAvailable      : 1;          // True once available.
     bool isScheduled      : 1;          // True once scheduled.
@@ -266,6 +266,7 @@ namespace llvm {
       : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
         Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
         isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+        hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isCloned(false),
         isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
@@ -277,6 +278,18 @@ namespace llvm {
       : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
         Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
         isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+        hasPhysRegClobbers(false),
+        isPending(false), isAvailable(false), isScheduled(false),
+        isScheduleHigh(false), isCloned(false),
+        isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
+        CopyDstRC(NULL), CopySrcRC(NULL) {}
+
+    /// SUnit - Construct a placeholder SUnit.
+    SUnit()
+      : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0),
+        Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
+        isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
+        hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isCloned(false),
         isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
@@ -416,10 +429,8 @@ namespace llvm {
 
   class ScheduleDAG {
   public:
-    SelectionDAG *DAG;                    // DAG of the current basic block
-    MachineBasicBlock *BB;                // Current basic block
-    MachineBasicBlock::iterator Begin;    // The beginning of the range to be scheduled.
-    MachineBasicBlock::iterator End;      // The end of the range to be scheduled.
+    MachineBasicBlock *BB;                // The block in which to insert instructions.
+    MachineBasicBlock::iterator InsertPos;// The position to insert instructions.
     const TargetMachine &TM;              // Target processor
     const TargetInstrInfo *TII;           // Target instruction information
     const TargetRegisterInfo *TRI;        // Target processor register info
@@ -430,6 +441,8 @@ namespace llvm {
     std::vector<SUnit*> Sequence;         // The schedule. Null SUnit*'s
                                           // represent noop instructions.
     std::vector<SUnit> SUnits;            // The scheduling units.
+    SUnit EntrySU;                        // Special node for the region entry.
+    SUnit ExitSU;                         // Special node for the region exit.
 
     explicit ScheduleDAG(MachineFunction &mf);
 
@@ -440,12 +453,9 @@ namespace llvm {
     ///
     void viewGraph();
   
-    /// Run - perform scheduling.
+    /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
+    /// according to the order specified in Sequence.
     ///
-    void Run(SelectionDAG *DAG, MachineBasicBlock *MBB,
-             MachineBasicBlock::iterator Begin,
-             MachineBasicBlock::iterator End);
-
     virtual MachineBasicBlock *EmitSchedule() = 0;
 
     void dumpSchedule() const;
@@ -467,6 +477,10 @@ namespace llvm {
 #endif
 
   protected:
+    /// Run - perform scheduling.
+    ///
+    void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
+
     /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
     /// to form the scheduling dependency graph.
     ///