Delete an unused function.

[oota-llvm.git] / include / llvm / CodeGen / ScheduleDAG.h

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 955965bccfa93ae104e472afe16b1a74e1ce5ea3..d53d60504c1bde4e0cb4dbe4c76b4b6b3051c24a 100644 (file)
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -27,7 +27,6 @@ namespace llvm {
   class SUnit;
   class MachineConstantPool;
   class MachineFunction;
-  class MachineModuleInfo;
   class MachineRegisterInfo;
   class MachineInstr;
   class TargetRegisterInfo;
@@ -227,6 +226,7 @@ namespace llvm {
   private:
     SDNode *Node;                       // Representative node.
     MachineInstr *Instr;                // Alternatively, a MachineInstr.
+    MachineInstr *DbgInstr;             // A dbg_value referencing this.
   public:
     SUnit *OrigNode;                    // If not this, the node from which
                                         // this node was cloned.
@@ -269,10 +269,10 @@ namespace llvm {
     /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
     /// an SDNode and any nodes flagged to it.
     SUnit(SDNode *node, unsigned nodenum)
-      : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
-        Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
-        isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
-        hasPhysRegClobbers(false),
+      : Node(node), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(nodenum),
+        NodeQueueId(0),  Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
+        NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
+        hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isCloned(false),
         isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
@@ -281,10 +281,10 @@ namespace llvm {
     /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
     /// a MachineInstr.
     SUnit(MachineInstr *instr, unsigned nodenum)
-      : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
-        Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
-        isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
-        hasPhysRegClobbers(false),
+      : Node(0), Instr(instr), DbgInstr(0), OrigNode(0), NodeNum(nodenum),
+        NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
+        NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
+        hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isCloned(false),
         isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
@@ -292,10 +292,10 @@ namespace llvm {
 
     /// SUnit - Construct a placeholder SUnit.
     SUnit()
-      : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0),
-        Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
-        isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
-        hasPhysRegClobbers(false),
+      : Node(0), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(~0u),
+        NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
+        NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
+        hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isCloned(false),
         isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
@@ -329,6 +329,20 @@ namespace llvm {
       return Instr;
     }
 
+    /// setDbgInstr - Assign the debug instruction for the SUnit.
+    /// This may be used during post-regalloc scheduling.
+    void setDbgInstr(MachineInstr *MI) {
+      assert(!Node && "Setting debug MachineInstr of SUnit with SDNode!");
+      DbgInstr = MI;
+    }
+
+    /// getDbgInstr - Return the debug MachineInstr for this SUnit.
+    /// This may be used during post-regalloc scheduling.
+    MachineInstr *getDbgInstr() const {
+      assert(!Node && "Reading debug MachineInstr of SUnit with SDNode!");
+      return DbgInstr;
+    }
+
     /// addPred - This adds the specified edge as a pred of the current node if
     /// not already.  It also adds the current node as a successor of the
     /// specified node.
@@ -445,7 +459,6 @@ namespace llvm {
     const TargetLowering *TLI;            // Target lowering info
     MachineFunction &MF;                  // Machine function
     MachineRegisterInfo &MRI;             // Virtual/real register map
-    MachineConstantPool *ConstPool;       // Target constant pool
     std::vector<SUnit*> Sequence;         // The schedule. Null SUnit*'s
                                           // represent noop instructions.
     std::vector<SUnit> SUnits;            // The scheduling units.