Increase ISD::ParamFlags to 64 bits. Increase the ByValSize

[oota-llvm.git] / include / llvm / CodeGen / ScheduleDAG.h

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 37c0a9032a26393a007da3f1741afb0cc840da1e..e86d08492aa212deda052a5daab827e4c439cff7 100644 (file)
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -24,10 +24,11 @@ namespace llvm {
   struct InstrStage;
   struct SUnit;
   class MachineConstantPool;
+  class MachineFunction;
   class MachineModuleInfo;
   class MachineRegisterInfo;
   class MachineInstr;
-  class MRegisterInfo;
+  class TargetRegisterInfo;
   class SelectionDAG;
   class SelectionDAGISel;
   class TargetInstrInfo;
@@ -242,7 +243,8 @@ namespace llvm {
     MachineBasicBlock *BB;                // Current basic block
     const TargetMachine &TM;              // Target processor
     const TargetInstrInfo *TII;           // Target instruction information
-    const MRegisterInfo *MRI;             // Target processor register info
+    const TargetRegisterInfo *TRI;        // Target processor register info
+    MachineFunction *MF;                  // Machine function
     MachineRegisterInfo &RegInfo;         // Virtual/real register map
     MachineConstantPool *ConstPool;       // Target constant pool
     std::vector<SUnit*> Sequence;         // The schedule. Null SUnit*'s
@@ -270,6 +272,7 @@ namespace llvm {
     ///
     static bool isPassiveNode(SDNode *Node) {
       if (isa<ConstantSDNode>(Node))       return true;
+      if (isa<ConstantFPSDNode>(Node))     return true;
       if (isa<RegisterSDNode>(Node))       return true;
       if (isa<GlobalAddressSDNode>(Node))  return true;
       if (isa<BasicBlockSDNode>(Node))     return true;
@@ -277,6 +280,7 @@ namespace llvm {
       if (isa<ConstantPoolSDNode>(Node))   return true;
       if (isa<JumpTableSDNode>(Node))      return true;
       if (isa<ExternalSymbolSDNode>(Node)) return true;
+      if (isa<MemOperandSDNode>(Node))     return true;
       return false;
     }
 
@@ -310,11 +314,16 @@ namespace llvm {
     /// (which do not go into the machine instrs.)
     static unsigned CountResults(SDNode *Node);
 
-    /// CountOperands  The inputs to target nodes have any actual inputs first,
-    /// followed by an optional chain operand, then flag operands.  Compute the
-    /// number of actual operands that  will go into the machine instr.
+    /// CountOperands - The inputs to target nodes have any actual inputs first,
+    /// followed by special operands that describe memory references, then an
+    /// optional chain operand, then flag operands.  Compute the number of
+    /// actual operands that will go into the resulting MachineInstr.
     static unsigned CountOperands(SDNode *Node);
 
+    /// ComputeMemOperandsEnd - Find the index one past the last
+    /// MemOperandSDNode operand
+    static unsigned ComputeMemOperandsEnd(SDNode *Node);
+
     /// EmitNode - Generate machine code for an node and needed dependencies.
     /// VRBaseMap contains, for each already emitted node, the first virtual
     /// register number for the results of the node.
@@ -355,6 +364,8 @@ namespace llvm {
     void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
                     const TargetInstrDesc *II,
                     DenseMap<SDOperand, unsigned> &VRBaseMap);
+
+    void AddMemOperand(MachineInstr *MI, const MemOperand &MO);
   };
 
   /// createBURRListDAGScheduler - This creates a bottom up register usage