Add DebugLoc to the getNode() methods.

[oota-llvm.git] / include / llvm / CodeGen / ScheduleDAGSDNodes.h

diff --git a/include/llvm/CodeGen/ScheduleDAGSDNodes.h b/include/llvm/CodeGen/ScheduleDAGSDNodes.h
index fa78faaecddd947d447f54603066653738cc86fe..8950433062f55d26aa39ca450b10eee6b2313355 100644 (file)
--- a/include/llvm/CodeGen/ScheduleDAGSDNodes.h
+++ b/include/llvm/CodeGen/ScheduleDAGSDNodes.h
@@ -17,54 +17,25 @@
 
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/ADT/SmallSet.h"
 
 namespace llvm {
-  /// HazardRecognizer - This determines whether or not an instruction can be
-  /// issued this cycle, and whether or not a noop needs to be inserted to handle
-  /// the hazard.
-  class HazardRecognizer {
-  public:
-    virtual ~HazardRecognizer();
-    
-    enum HazardType {
-      NoHazard,      // This instruction can be emitted at this cycle.
-      Hazard,        // This instruction can't be emitted at this cycle.
-      NoopHazard     // This instruction can't be emitted, and needs noops.
-    };
-    
-    /// getHazardType - Return the hazard type of emitting this node.  There are
-    /// three possible results.  Either:
-    ///  * NoHazard: it is legal to issue this instruction on this cycle.
-    ///  * Hazard: issuing this instruction would stall the machine.  If some
-    ///     other instruction is available, issue it first.
-    ///  * NoopHazard: issuing this instruction would break the program.  If
-    ///     some other instruction can be issued, do so, otherwise issue a noop.
-    virtual HazardType getHazardType(SDNode *) {
-      return NoHazard;
-    }
-    
-    /// EmitInstruction - This callback is invoked when an instruction is
-    /// emitted, to advance the hazard state.
-    virtual void EmitInstruction(SDNode *) {}
-    
-    /// AdvanceCycle - This callback is invoked when no instructions can be
-    /// issued on this cycle without a hazard.  This should increment the
-    /// internal state of the hazard recognizer so that previously "Hazard"
-    /// instructions will now not be hazards.
-    virtual void AdvanceCycle() {}
-    
-    /// EmitNoop - This callback is invoked when a noop was added to the
-    /// instruction stream.
-    virtual void EmitNoop() {}
-  };
-
+  /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
+  /// 
+  /// Edges between SUnits are initially based on edges in the SelectionDAG,
+  /// and additional edges can be added by the schedulers as heuristics.
+  /// SDNodes such as Constants, Registers, and a few others that are not
+  /// interesting to schedulers are not allocated SUnits.
+  ///
+  /// SDNodes with MVT::Flag operands are grouped along with the flagged
+  /// nodes into a single SUnit so that they are scheduled together.
+  ///
+  /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
+  /// edges.  Physical register dependence information is not carried in
+  /// the DAG and must be handled explicitly by schedulers.
+  ///
   class ScheduleDAGSDNodes : public ScheduleDAG {
   public:
-    SmallSet<SDNode*, 16> CommuteSet;     // Nodes that should be commuted.
-
-    ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
-                       const TargetMachine &tm);
+    explicit ScheduleDAGSDNodes(MachineFunction &mf);
 
     virtual ~ScheduleDAGSDNodes() {}
 
@@ -88,7 +59,14 @@ namespace llvm {
     /// NewSUnit - Creates a new SUnit and return a ptr to it.
     ///
     SUnit *NewSUnit(SDNode *N) {
+#ifndef NDEBUG
+      const SUnit *Addr = 0;
+      if (!SUnits.empty())
+        Addr = &SUnits[0];
+#endif
       SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
+      assert((Addr == 0 || Addr == &SUnits[0]) &&
+             "SUnits std::vector reallocated on the fly!");
       SUnits.back().OrigNode = &SUnits.back();
       return &SUnits.back();
     }
@@ -100,10 +78,11 @@ namespace llvm {
     
     virtual SelectionDAG *getDAG() { return DAG; }
 
-    /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
-    /// This SUnit graph is similar to the SelectionDAG, but represents flagged
-    /// together nodes with a single SUnit.
-    virtual void BuildSchedUnits();
+    /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
+    /// are input.  This SUnit graph is similar to the SelectionDAG, but
+    /// excludes nodes that aren't interesting to scheduling, and represents
+    /// flagged together nodes with a single SUnit.
+    virtual void BuildSchedGraph();
 
     /// ComputeLatency - Compute node latency.
     ///
@@ -128,7 +107,7 @@ namespace llvm {
     /// VRBaseMap contains, for each already emitted node, the first virtual
     /// register number for the results of the node.
     ///
-    void EmitNode(SDNode *Node, bool IsClone,
+    void EmitNode(SDNode *Node, bool IsClone, bool HasClone,
                   DenseMap<SDValue, unsigned> &VRBaseMap);
     
     virtual MachineBasicBlock *EmitSchedule();
@@ -165,12 +144,17 @@ namespace llvm {
     /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
     /// implicit physical register output.
     void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
-                         unsigned SrcReg,
+                         bool IsCloned, unsigned SrcReg,
                          DenseMap<SDValue, unsigned> &VRBaseMap);
     
     void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
-                                const TargetInstrDesc &II,
+                                const TargetInstrDesc &II, bool IsClone,
+                                bool IsCloned,
                                 DenseMap<SDValue, unsigned> &VRBaseMap);
+
+    /// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
+    void BuildSchedUnits();
+    void AddSchedEdges();
   };
 }